Low complexity soft-decision demapper for high order modulation of DVB-S2 system

Park, Jang Woong; Sunwoo, Myung Hoon; Kim, Pan Soo; Chang, Dae-Ig

doi:10.1109/socdc.2008.4815678

Cited by 11 publications

(10 citation statements)

References 5 publications

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“…Table 6 summarizes the comparison of the proposed demapper architecture with relevant state-of-the-art implementations in terms of utilized resources and performance. The presented demapper architectures in [27] and [28] are dedicated to certain wireless communication standards. In [27], where the conventional RTL design approach has been used, DVB-T2is the target standard; hence, the architecture design supports the QPSK, 16-QAM, 64-QAM and 256-QAM modulation schemes for non-GrayDVB constellation with rotation.…”

Section: Throughput Resultsmentioning

confidence: 99%

“…In [27], where the conventional RTL design approach has been used, DVB-T2is the target standard; hence, the architecture design supports the QPSK, 16-QAM, 64-QAM and 256-QAM modulation schemes for non-GrayDVB constellation with rotation. Similarly, the architecture described in [28] has been designed to fulfill the requirements of the DVB-S2 standard. Four modulation schemes are supported (QPSK, 8-PSK, 16-PSK and 32-PSK) with Gray mapping constellation, as specified in [29].…”

Section: Throughput Resultsmentioning

confidence: 99%

“…In [28], the timing information about the hardware implementation is not available. Only device utilization is presented.…”

Section: Demapper Modulementioning

confidence: 99%

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Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

et al. 2016

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In the domain of digital wireless communication, flexible design implementations are increasingly explored for different applications in order to cope with diverse system configurations imposed by the emerging wireless communication standards. In fact, shrinking the design time to meet market pressure, on the one hand, and adding the emerging flexibility requirement and, hence, increasing system complexity, on the other hand, require a productive design approach that also ensures final design quality. The no instruction set computer (NISC) approach fulfills these design requirements by eliminating the instruction set overhead. The approach offers static scheduling of the datapath, automated register transfer language (RTL)synthesis and allows the designer to have direct control of hardware resources. This paper presents a complete NISC-based design and prototype flow, from architecture specification till FPGA implementation. The proposed design and prototype flow is illustrated through two case studies of flexible implementations, which are dedicated to low-complexity MIMO turbo-equalizer and a universal turbo-demapper. Moreover, the flexibility of the proposed prototypes allows supporting all communication modes defined in the emerging wireless communication standards, such LTE, LTE-Advanced, WiMAX, WiFi and DVB-RCS. For each prototype, its functionality is evaluated, and the resultant performance is verified for all system configurations.

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Section: Throughput Resultsmentioning

confidence: 99%

Section: Throughput Resultsmentioning

confidence: 99%

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Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

et al. 2016

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“…2 (21) and e m 2 ,k i,j denotes the index of the corresponding radius calculated by (12). For example, for case ii), we have e can be recursively determined from e…”

Section: ) Performance Analysismentioning

confidence: 99%

“…A simplified demapper is also proposed for multilevel coding followed by multistage decoding, which focuses on the APSK signal [11], and the complexity of this APSK demapper is reduced to a constant (neglecting comparison operations) at the cost of exponentially increasing the memory required and necessitating an additional division [11]. In [12], the complexity of the demapper is reduced by reusing the multipliers, and only 16 multipliers are used for all the four modulation modes (QPSK, 8PSK, 16APSK, and 32APSK) in the second-generation digital video broadcasting over satellite (DVB-S2) system. For the constellation rotation and cyclic Q delay modulation of DVB-T2, several simplified demappers are proposed for reducing 0018-9545 © 2013 IEEE.…”

Section: Introductionmentioning

confidence: 99%

A Universal Low-Complexity Symbol-to-Bit Soft Demapper

Wang

Xie

Hanzo

et al. 2014

IEEE Trans. Veh. Technol.

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Abstract-High-order constellations are commonly used for achieving high bandwidth efficiency in most communication systems. However, the complexity of the multiplication operations associated with the standard max-sum approximation of the maximum a posteriori probability in the log-domain (Max-Log-MAP) symbol-to-bit demapper is very high. In this contribution, we conceive a low-complexity universal soft demapper, which reduces the demapper's complexity considerably for the binary-reflected Gray-labeled pulse amplitude modulation (PAM), phase shift keying (PSK), quadrature amplitude modulation (QAM), and amplitude phase-shift keying (APSK) relying on product constellation labeling (product-APSK). Our theoretical analysis demonstrates that the proposed demapper has exactly the same performance as the Max-Log-MAP demapper for the Gray-labeled PAM, PSK, and QAM. Our theoretical analysis and simulation results also demonstrate that for the Gray-labeled product-APSK, the performance degradation of the proposed simplified soft demapper is negligible for both 64-ary and 256-ary constellations compared with the Max-Log-MAP demapper.Index Terms-Amplitude phase-shift keying (APSK), Max-Log-MAP, phase-shift keying (PSK), pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), soft demapper.

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A Novel Simplified Log-Likelihood Ratio for Soft-Output Demapping of CMMB

Sun

Zeng

2011

Communications in Computer and Information Science

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Low complexity soft-decision demapper for high order modulation of DVB-S2 system

Cited by 11 publications

References 5 publications

Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

A Universal Low-Complexity Symbol-to-Bit Soft Demapper

A Novel Simplified Log-Likelihood Ratio for Soft-Output Demapping of CMMB

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