Low complexity semi–systolic multiplication architecture over <i>GF</i>(2<i>^m</i>)

Abstract

This paper presents a semi-systolic Montgomery multiplier based on the redundant basis representation of the finite field elements. The proposed multiplier has less hardware and time complexities compared to related multipliers. We also propose a serial systolic Montgomery multiplier that can be applied well in space-limited hardware. Furthermore, a simple inversion based on the proposed scheme is presented.

Reduced complexity polynomial multiplier architecture for finite fields <i>GF</i>(2<i>^m</i>)

“…As a result, efficient multipliers with low complexity are important from the perspective of system performance. A number of systolic multipliers over GFð2 m Þ have been introduced [3,4,5,6,7]. Lee et al [3] and Chiou et al [4] proposed a semi-systolic multiplier with concurrent error detection.…”

“…Kim-Kim [6] proposed a time efficient semi-systolic multiplier. Recently, Choi-Lee [7] proposed an area and time efficient semi-systolic multiplier based on the redundant basis. However, their high circuit complexities and long propagation delays are crucial limitations in cryptographic applications.…”

Efficient systolic modular multiplier/squarer for fast exponentiation over <i>GF</i>(2<i>^m</i>)

“…As a result, efficient multipliers are important from a system performance point of view. Although several multipliers have been developed with a polynomial basis of GFð2 m Þ, their high space and time complexities are major limitations in cryptographic applications [1,2,3,4]. Thus, further research on efficient multiplication architectures with low space and time complexities is required.…”

A semi-systolic Montgomery multiplier over <i>GF</i>(2<i>^m</i>)

“…Three different multipliers, namely the bit-serial, digit-serial, and bit-parallel multipliers, have been considered and the concurrent error detection scheme has been derived and implemented for each of them. Many semi-systolic multiplier over GFð2 m Þ have been developed [7,8,9,10].…”

“…Kim and Kim [9] proposed an area-efficient multiplier than multipliers proposed in [7,8]. Recently, Choi and Lee [10] proposed a low complexity semi-systolic multiplier based on the redundant basis representation of the finite field elements. In this paper, we induce an efficient multiplication algorithm for reduction of hardware complexity of typical architectures.…”