Reduced complexity polynomial multiplier architecture for finite fields <i>GF</i>(2<i>^m</i>)

Abstract

This letter presents a low-complexity semi-systolic array implementation for polynomial multiplication over GF(2 m ). We consider finite field Montgomery modular multiplication (MMM) based on two-level parallel computing approach to reduce the cell delay, latency, and area-time (AT) complexity. Compared to related multipliers, the proposed scheme yields significantly lower AT complexity.

Low-latency semi-systolic architecture for multiplication over finite fields

“…But our multiplier has the least time and area-time complexity among multipliers in Table I and its throughput is 1. Although the area complexity of our multiplier is nearly the same with Kim-Kim [15], our multiplier saves about 64.9%, 49.9%, and 50.0% time complexities as compared to Huang [13], Kim-Kim [15], and Choi-Lee [24], respectively. Considering AT (area-time) complexity, our multiplier saves about 68.1%, 49.7%, and 23.7% as compared to Huang [13], Kim-Kim [15], and Choi-Lee [24], respectively.…”

“…A comparison between the proposed and the related semi-systolic multipliers is given in Table I. Although Choi-Lee's multiplier [24] has the least area complexity among multipliers in Table I, its throughput is 1/2. But our multiplier has the least time and area-time complexity among multipliers in Table I and its throughput is 1.…”

“…Thus, an efficient multiplication architecture with low complexity is needed to design dedicated high-speed circuits. Various architectures for arithmetic over GFð2 m Þ have been developed [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25].…”