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In this study, we present an efficient finite field arithmetic architecture based on systolic array for multiplication which is a core algorithm for division and exponentiation operations. In order to obtain dedicated area-efficient circuits, we adopt Montgomery multiplication algorithm and systolic array. First of all we induce an efficient arithmetic algorithm from typical Montgomery multiplication using an effective factor, then we design an efficient semi-systolic array based multiplication architecture which is highly suitable for pipelined operations. The proposed multiplier saves at least 40% area complexity as compared to the corresponding existing structures.

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This paper presents a decoder with enable input. This decoder is developed using quantum-dot cellular automata (QCA)

A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.