Low-Capacitance Low-Voltage Triggered SCR ESD Clamp Using nMOS With Asymmetric Drain for RF ICs

Park, Jae Young; Kim, Dae Woo; Son, Young-Sang; Ha, Jong-Chan; Song, Jong-Kyu; Jang, Chang-Soo; Jung, Wonjin

doi:10.1109/tmtt.2010.2086067

Cited by 2 publications

(2 citation statements)

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“…If we modify our expressions for gain according to this we have (32) This extension of our analysis would result in somewhat lower bounds but will not change our general conclusions. The threshold for a total gain where it is appropriate to switch from a design with stages to a design with stages in a cascade is (33) Thus a two stage amplifier should be considered when the total voltage gain exceeds 4 . The TRF receiver has its amplification concentrated to the LNA, and the here treated receivers use a maximum gain of before the antenna noise limits the sensitivity.…”

Section: Discussionmentioning

confidence: 99%

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Power Consumption of Integrated Low-Power Receivers

Nilsson

Svensson

2014

IEEE J. Emerg. Sel. Topics Circuits Syst.

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With the advent of Internet of Things (IoT) it has become clear that radio-frequency (RF) designers have to be aware of power constraints, e.g., in the design of simplistic ultra-low power receivers often used as wake-up radios (WuRs). The objective of this work, one of the first systematic studies of power bounds for RF-systems, is to provide an overview and intuitive feel for how power consumption and sensitivity relates for low-power receivers. This was done by setting up basic circuit schematics for different radio receiver architectures to find analytical expressions for their output signal-to-noise ratio including power consumption, bandwidth, sensitivity, and carrier frequency. The analytical expressions and optimizations of the circuits give us relations between dc-energy-per-bit and receiver sensitivity, which can be compared to recent published low-power receivers. The parameter set used in the analysis is meant to reflect typical values for an integrated 90 nm complementary metal-oxide-semiconductor fabrication processes, and typical small sized RF lumped components.Index Terms-Complementary metal-oxide-semiconductor (CMOS), Internet of things (IoT), low noise, low-power, receiver, wake-up radio (WuR).

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Section: Discussionmentioning

confidence: 99%

“…Further, the loading capacitance of an ASIC bond pad end up at around 400 fF when ESD protection is included. However, here we assume that we may reduce the load to 75 fF, reflecting the ongoing development of RF ESD clamps [33].…”

Section: Description Of Parameter Set and Analysismentioning

confidence: 99%