Longest path selection for delay test under process variation

Lü, Xiang; Li, Z.; Qiu, Wangqi; Walker, D.M.H.; Shi, Weiping

doi:10.1109/aspdac.2004.1337547

Cited by 25 publications

(24 citation statements)

References 15 publications

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“…The impact of process variation on delay fault testing of ICs has recently received increased attention [147,143,148,149,150,151]. Process variation tends to affect gate-delay and subsequently path-delay and can change the ratio between rise-time and fall-time for a gate.…”

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

“…A consequence of such variation is that it is difficult to determine the delay that is associated with the signal paths through the circuit. The problem of determining the longest path in terms of delay under process variation has been addressed in [147,148,149,151]. In the presence of process variation, a path through a net is said to be longest, for that net, if there exists a configuration of IC parameter values for which the path has the maximum delay among all paths through the net [149].…”

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

“…The problem of determining the longest path in terms of delay under process variation has been addressed in [147,148,149,151]. In the presence of process variation, a path through a net is said to be longest, for that net, if there exists a configuration of IC parameter values for which the path has the maximum delay among all paths through the net [149]. So for each net, there can be multiple paths that each is longest under different configurations of the IC parameters.…”

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

See 2 more Smart Citations

Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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The final part studies the impact of process variation on the behaviour of bridge defects.Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation.

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Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

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Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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“…Recent research has reported that process variation has an impact on manufacturing test quality. The work in [3]- [6] considered the effect of process variation on at-speed and delay test, addressing the issues of calculating delay as a function of process variables [5], identification of the longest path [3], [6] and calculation of a test response capture time that tolerates variation [4]. This paper addresses the impact of process variation on static defects with focus on resistive bridging faults.…”

Section: Introductionmentioning

confidence: 99%

Process Variation-Aware Test for Resistive Bridges

Ingelsson

Al-Hashimi

Khursheed

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper analyses the behaviour of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesised ISCAS benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation.

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“…To address the effect, great amount of research has been done recently, such as the clock skew analysis under process variation [4][5][6][7][8][9][10], statistical performance analysis [9,10], worst case performance analysis [11,12], parametric yield estimation [12,13], impact analysis on micro architecture [12,13] and delay fault [14,15] test under process variation [14][15][16][17]. As the technology reaches deep submicron or nanometer regime, the errors due to process variations becomes prominent [17][18][19]. Threshold voltage of a MOSFET varies due to (1) Changes in oxide thickness; (2) Substrate, polysilicon and implant impurity level; (3) Surface charge.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Propagation Delay Deviation under Process Induced Threshold Voltage Variation

Verma¹,

Kaushik²,

Singh³

2011

IJCA

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Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The primary sources of manufacturing variation include Deposition, Chemical Mechanical Planarization (CMP), Etching, Resolution Enhancement Technology (RET). Process variations manifest themselves as the uncertainties of circuit performance, such as delay, noise and power consumption. The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-100-nm scale. The reduced predictability can be attributed to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. Threshold voltage of a MOSFET varies due to changes in oxide thickness; substrate, polysilicon and implant impurity level; and surface charge. This paper provides a comprehensive analysis of the effect of threshold variation on the propagation delay through driver-interconnect-load (DIL) system. The impact of process induced threshold variations on circuit delay is discussed for three different technologies i.e 130nm, 70nm and 45nm. The comparison of results between these three technologies shows that as device size shrinks, the process variation issues becomes dominant during design cycle and subsequently increases the uncertainty of the delays.

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Longest path selection for delay test under process variation

Cited by 25 publications

References 15 publications

Investigation into voltage and process variation-aware manufacturing test

Investigation into voltage and process variation-aware manufacturing test

Process Variation-Aware Test for Resistive Bridges

Analysis of Propagation Delay Deviation under Process Induced Threshold Voltage Variation

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