Abstract:Long-range dependence is a property of stochastic processes that has an important impact on network performance, especially on the buffer usage in routers. We analyze the presence of long-range dependence in on-chip processor traffic and we study the impact of long-range dependence on networks-on-chip. We propose to investigate the presence of long-range dependence in communication traces of processor ips at the cycle-accurate level. We also study the impact of long-range dependence on a real network-on-chip u… Show more
“…Hu et al [41] has presented a non-uniform NoC buffer space allocation algorithm under various random traffic patterns. In [42] long-range dependencies and analysis the real traffic patterns and buffer sizing problems are studied.…”
“…Hu et al [41] has presented a non-uniform NoC buffer space allocation algorithm under various random traffic patterns. In [42] long-range dependencies and analysis the real traffic patterns and buffer sizing problems are studied.…”
“…Usually, these topologies have to face non-uniform traffic resulting from several factors, such as routing biases, topological artifacts, long-range dependencies, traffic scenarios, and many others. Such nonuniform traffic has a vital influence on the performance of NoC topologies that have been widely studied by [19,20,95], this non-uniformity of network traffic results in local congested regions that increases network delay and lower NoC performance. The functionality of a routing method can be divided into two parts: the route computation and selection functions, as shown in fig 1 . The route computation function provides the route from the current router to the destination router FIGURE 1: The selection strategy uses network congestion information to select one direction out of directions received from routing algorithms.…”
Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. Network-on-Chip (NoC) is a scalable and promising interconnection solution used by MPSoCs to achieve high performance. Routing algorithms provide a path to a packet toward the destination. For this, these algorithms should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews the selection strategies used to reduce congestion in NoC and classifies them on the technique adopted to handle and propagate congestion information. Additionally, this paper provides the implementation and analysis details of some state-of-art selection methods.
“…Recent measurements of on-chip traffic [15], [16], [21] have convincingly shown that scale-invariant burstiness (i.e. self-similarity [12]) is being recognized in both pair-wised single application [21] and over entire network [16].…”
Section: Introductionmentioning
confidence: 99%
“…self-similarity [12]) is being recognized in both pair-wised single application [21] and over entire network [16].…”
Section: Introductionmentioning
confidence: 99%
“…The authors in [15], [16] extended the results of [21] to cycle-accurate level and proposed a stochastic traffic generator being aware that 1) On-chip traffic is non-stationary 2) On-chip traffic flows contain long range dependent behavior that must be taken into account when synthesizing traffic. Recently, the authors in [18] propose an empiricallyderived network on-chip traffic model for homogeneous NoCs.…”
Designing appropriate buffer sizes for routers within Network-on-Chip (NoC) so as to minimize the power while preserving the required performance in the presence of self-similar traffic has been considered a challenging problem in the literature. A few analytical studies carried out in NoC modeling have been adopted assumptions such as exponentiallydistributed packet inter-arrivals, and conclusions reached under such assumptions may be inappropriate in the presence of self-similar traffic. Through mathematical analysis this paper predicts the optimal buffer size under self-similar traffic using Discrete Poisson Pareto Burst Process (DPPBP). The validity of the mathematical expressions is demonstrated through simulation experiments.
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