Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm

Liu, Peng; You, Zhiqiang; Kuang, Jishun; Hu, Zhaoyang; Wang, Weizheng

doi:10.1587/elex.12.20150839

Cited by 10 publications

(12 citation statements)

References 7 publications

(14 reference statements)

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“…Timing optimization for logic circuits is one of the most important requirements during logic synthesis [1][2][3][4]. The industry's mainstream electronic design automation (EDA) tool for logic synthesis is Design Compiler (DC) produced by Synopsys5.…”

Section: Introductionmentioning

confidence: 99%

Novel Verification Method for Timing Optimization Based on DPSO

et al. 2018

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Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.

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Section: Introductionmentioning

confidence: 99%

Novel Verification Method for Timing Optimization Based on DPSO

et al. 2018

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“…Then this scheme was enhanced for multilevel memristor memories [6]. In [7], based logic operation a DFT architecture for 1R cross‐bar testing was proposed, where memristor‐aided logic NOR gates are embedded to check whether all the cells in the cross‐bar are 0 s or not at a time. A March‐like test algorithm was presented for the proposed architecture achieving short test time with a little area overhead.…”

Section: Introductionmentioning

confidence: 99%

“…A number of fault models and test methods are proposed to test one memristor (1R) cross-bar [3][4][5][6][7] and one transistor 1R (1T1R) cross-bar [8]. Haron et al [3] proposed stuck-at fault, transition fault (TF) and undefined state faults (USFs) considering open, bridge and short defects in 1R cross-bar.…”

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confidence: 99%

Efficient March test algorithm for 1T1R cross‐bar with complete fault coverage

et al. 2016

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As an attractive option of future non-volatile memories, resistive RAM (RRAM) has attracted more attentions. Among RRAM architectures, one transistor one memristor (1T1R) crossbar is the most fledged one. A March C*-1T1R algorithm is proposed for 1T1R crossbar. The pass-fail fault dictionary of the proposed March test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors, transistors and their interconnecting wires with a little test time overhead compared with previous methods. Stuck-at 1 (SA1): These faults can be sensitised by w0 and detected by r0. The faults are sensitised by M1, M3 or M5 and detected by M2, M4 or M6. SA0: These faults can be sensitised by w1 and detected by r1. The faults are sensitised by M2 or M4 and detected by M3 or M5. Deep-0: These faults can be initialised by two w0, be sensitised by w1 and detected by r1. Since the memristor of 1T1R crossbar undergoes a forming process, all memristors are initiated into LRS. The values of all 1T1R cells are logic 0 s. After forming operation, that is the first w0, M1 initialises the faults in the crossbar as the second w0. M2 sensitises the faults. Then, the faults can be detected by M3. Deep-1: These faults can be initialised by two w1, be sensitised by w0 and detected by r0. M4 initialises the faults as the first w1. M5 initialises the faults as the second w1. M5 also sensitises the faults. Then, the faults can be detected by M6. Deep-1/0: These faults have the characteristics of both Deep-1 and Deep-0 faults. Therefore, the test method of either Deep-1 or Deep-0 is also effective in detecting these faults. Slow Write 0 (SW0): These faults can be initialised by w1, sensitised by w0, and detected by r0. M2 or M5 initialises the faults. M3 or M5 sensitises the faults. Then, the faults can be detected by M4 or M6. SW1: These faults can be initialised by w0, sensitised by w1, and detected by r1. M1 or M3 initialises the faults. M2 or M4 sensitises the faults. Then, the faults can be detected by M3 or M5. R1D: During a read operation, if the data of a cell is flipped from logic 1 to logic 0, the cell has an R1D fault [8]. For these faults, there can be sensitised by r1 and detected by another succession of r1. In our March test algorithm, M3 sensitises and detects the faults. State CF (CFst): The CFst is defined that a victim cell is forced to a certain value only if the aggressor cell is in a given state. Therefore, there are four kinds of CFsts: CFst(0;0), CFst(0;1), CFst(1;0) and CFst(1;1). The first parameter in the parentheses represents for the operation of aggressor cell and the second parameter represents for the state of victim. In our March test algorithm, w1 in M2 initialises CFst(0;0). w0 in M3 sensitises CFst(0;0). r1 in M3 detects the CFst(0;0) in the victim cell which has lower address than the aggressor cell, named as CFst(0;0)>. In the similar way, CFst(0;0)<, CFst(1;1)< and CFst(1;1)>

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“…There are several works for fault models and test methods of 1R crossbar [1,2] and 1T1R crossbar [3,4]. In [1], Deep and Slow Write faults are proposed which considers the process deviation due to the fabrication of the memristor.…”

mentioning

confidence: 99%

“…We previously proposed a Design for Testability (DFT) method using memristor-aided logic (MAGIC) NOR operation for the 1R crossbar, which determines whether all memristors in 1R crossbar are 0 s or not simultaneously. A March-like test algorithm based on the proposed DFT is presented, which achieves short test time with a little area overhead [2]. In [4], March C*-1T1R test algorithm is proposed, which can detect the faults which consider the process deviation due to the fabrication of the memristor and the fault models in the traditional RAM testing.…”

mentioning

confidence: 99%

Logic operation‐based Design for Testability method and parallel test algorithm for 1T1R crossbar

et al. 2017

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Among resistive random access memory (RRAM) architectures, one transistor one memristor (1T1R) crossbar is the most fledged one. For 1T1R crossbar, a logic operation-based Design for Testability and parallel test algorithm, which is an improvement of March C*-1T1R test algorithm, are proposed. The pass-fail fault dictionary of the proposed test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors and traditional RAM. Compared with March MOM, March C* and March C*-1T1R, the test time of the proposed test algorithm is reduced with a little area overhead for a large size crossbar.

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Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm

Cited by 10 publications

References 7 publications

Novel Verification Method for Timing Optimization Based on DPSO

Novel Verification Method for Timing Optimization Based on DPSO

Efficient March test algorithm for 1T1R cross‐bar with complete fault coverage

Logic operation‐based Design for Testability method and parallel test algorithm for 1T1R crossbar

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