Efficient March test algorithm for 1T1R cross‐bar with complete fault coverage

Abstract

As an attractive option of future non-volatile memories, resistive RAM (RRAM) has attracted more attentions. Among RRAM architectures, one transistor one memristor (1T1R) crossbar is the most fledged one. A March C*-1T1R algorithm is proposed for 1T1R crossbar. The pass-fail fault dictionary of the proposed March test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors, transistors and their interconnecting wires with a little test time overhead compared with previous methods. Stuck-at 1 (SA1): These faults can be sensitised by w0 and detected by r0. The faults are sensitised by M1, M3 or M5 and detected by M2, M4 or M6. SA0: These faults can be sensitised by w1 and detected by r1. The faults are sensitised by M2 or M4 and detected by M3 or M5. Deep-0: These faults can be initialised by two w0, be sensitised by w1 and detected by r1. Since the memristor of 1T1R crossbar undergoes a forming process, all memristors are initiated into LRS. The values of all 1T1R cells are logic 0 s. After forming operation, that is the first w0, M1 initialises the faults in the crossbar as the second w0. M2 sensitises the faults. Then, the faults can be detected by M3. Deep-1: These faults can be initialised by two w1, be sensitised by w0 and detected by r0. M4 initialises the faults as the first w1. M5 initialises the faults as the second w1. M5 also sensitises the faults. Then, the faults can be detected by M6. Deep-1/0: These faults have the characteristics of both Deep-1 and Deep-0 faults. Therefore, the test method of either Deep-1 or Deep-0 is also effective in detecting these faults. Slow Write 0 (SW0): These faults can be initialised by w1, sensitised by w0, and detected by r0. M2 or M5 initialises the faults. M3 or M5 sensitises the faults. Then, the faults can be detected by M4 or M6. SW1: These faults can be initialised by w0, sensitised by w1, and detected by r1. M1 or M3 initialises the faults. M2 or M4 sensitises the faults. Then, the faults can be detected by M3 or M5. R1D: During a read operation, if the data of a cell is flipped from logic 1 to logic 0, the cell has an R1D fault [8]. For these faults, there can be sensitised by r1 and detected by another succession of r1. In our March test algorithm, M3 sensitises and detects the faults. State CF (CFst): The CFst is defined that a victim cell is forced to a certain value only if the aggressor cell is in a given state. Therefore, there are four kinds of CFsts: CFst(0;0), CFst(0;1), CFst(1;0) and CFst(1;1). The first parameter in the parentheses represents for the operation of aggressor cell and the second parameter represents for the state of victim. In our March test algorithm, w1 in M2 initialises CFst(0;0). w0 in M3 sensitises CFst(0;0). r1 in M3 detects the CFst(0;0) in the victim cell which has lower address than the aggressor cell, named as CFst(0;0)>. In the similar way, CFst(0;0)<, CFst(1;1)< and CFst(1;1)>

Logic operation‐based Design for Testability method and parallel test algorithm for 1T1R crossbar

“…In [4], March C*‐1T1R is proposed, which can detect all Stuck‐at 1 (SA1), SA0, Deep‐1, Deep‐0, SW1, SW0, R1D, address faults (AFs) and coupling fault (CF), including state coupling (CFst), idempotent coupling (CFid), inversion coupling (CFin). March C*‐1T1R is shown as follows: These fault models are classified into three kinds, namely, single‐cell faults, CFs and AFs.…”

“…There are several works for fault models and test methods of 1R crossbar [1,2] and 1T1R crossbar [3,4]. In [1], Deep and Slow Write faults are proposed which considers the process deviation due to the fabrication of the memristor.…”

“…A March-like test algorithm based on the proposed DFT is presented, which achieves short test time with a little area overhead [2]. In [4], March C*-1T1R test algorithm is proposed, which can detect the faults which consider the process deviation due to the fabrication of the memristor and the fault models in the traditional RAM testing.…”

“…Parallel march test algorithm: In [4], March C*-1T1R is proposed, which can detect all Stuck-at 1 (SA1), SA0, Deep-1, Deep-0, SW1, SW0, R1D, address faults (AFs) and coupling fault (CF), including state coupling (CFst), idempotent coupling (CFid), inversion coupling (CFin). March C*-1T1R is shown as follows:…”

The influence of temperature on set voltage for different high resistance state in 1T1R devices

“…According to previous research, the RRAM is suitable for being computing devices because of its high operation speed. [15][16][17][18][19] Due to the continuous computing, the temperature of the devices will rise. However, previous research indicates that the characteristics of RRAM will be affected by temperature.…”