Logic Design Within Memristive Memories Using Memristor-Aided loGIC (MAGIC)

Talati, Nishil; Gupta, Saransh; Mane, Pravin; Kvatinsky, Shahar

doi:10.1109/tnano.2016.2570248

Cited by 267 publications

(213 citation statements)

References 48 publications

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“…[5] The circuit I in Figure 1c shows the schematic structure of the IMP logic gate. www.advelectronicmat.de first IMP logic concept, several cognate resistance-represented logic concepts are proposed, such as the MAGIC logic [14,15] and the three-memristor stateful logic gate, [16] which all belong to the stateful logic family. The IMP logic operation can be achieved between the two original resistance states of memristors (logic inputs) and the final resistance state of one memristor (logic output) by triggering a conditional resistive switching process (conditional writing).…”

Section: Introductionmentioning

confidence: 99%

Fully Functional Logic‐In‐Memory Operations Based on a Reconfigurable Finite‐State Machine Using a Single Memristor

Yoon

Kim

et al. 2018

Adv Elect Materials

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resistance switching characteristic have been extended from the traditional nonvolatile memory [3] to the new computing paradigms. [4][5][6][7][8][9] A notable field is the memristor-based logic-in-memory (LIM) concept, which is capable of constructing an in-memory computation system by merging the function of the arithmetic logic unit (ALU) and memory, which are separated in the conventional von Neumann architecture. [10] Figure 1a illustrates the typical configuration of the conventional von Neumann computing machine. The machine is divided into three parts: the main memory, control unit, and ALU. The four-step machine cycles of fetching, decoding, executing, and storing are used to control the instruction and data streams for the performance of a computing process. The disparity of operation speed between the central processing unit (CPU, ALU + control unit) and the memory incurs operation delay, and the huge data transfer between the memory and the ALU, especially in data-intense tasks, consumes too much energy. This problem is called "von Neumann bottleneck," which is regarded as the fundamental limitations of the current computers. [11,12] This bottleneck can be addressed by performing computation steps within the memory block, which is called "in-memory computing (IMC)" or "logic-in-memory (LIM)." Figure 1b shows the schematic structure of such computational machines. When the ALU and memory are merged into a compact memory-ALU (MALU), the results can be saved while the commands are being executed. In this way, the storing step is omitted, leading to a highly energy-efficient computing paradigm. The memristor can provide fine-grained functionality support for the IMC machine because the logic output can be saved along with the logic operation when the LIM concept is adopted. This important feature may render the ideal IMC machine feasible. Figure 1c shows an approximate possible layout of the IMC machine, a kind of hybrid complementary metal-oxide-semiconductor (CMOS)/memristor crossbar architecture. The CMOS layer is used as the control unit whereas the memristor crossbar array layer and a small-amount CMOS auxiliary layer constitute MALU for LIM operations. This structure shares some of the features of the neuromorphic computation architecture based on memristors, [6] but it is not a network-based structure. Apparently, the memristor-based LIM Memristor offers a promising logic-in-memory (LIM) functionality to achieve the futuristic in-memory computing machine, which may solve the problem of the "von Neumann bottleneck" in the conventional computer architecture. A sequential logic concept is capable of achieving LIM based on the finitestate machine (FSM) using a single bipolar (BRS) or complementary resistive switching (CRS) memristor, where 14 of the 16 two-input Boolean logic functions (XOR and XNOR are missing) are mapped between the resistance state and the terminal voltages. In this paper, a new FSM-LIM concept based on a reconfigurable finite-state machine (RFSM logic) is proposed, which is experim...

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Section: Introductionmentioning

confidence: 99%

Fully Functional Logic‐In‐Memory Operations Based on a Reconfigurable Finite‐State Machine Using a Single Memristor

Yoon

Kim

et al. 2018

Adv Elect Materials

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“…Shafiee et al [54] developed ISAAC, an in-situ accelerator of neural networks, where memristor crossbar arrays are used to perform dotproduct operations in an analog manner. Kvatinsky et al [55] and Talati et al [56] developed MAGIC, a RRAM based in-data processing-in-memory architecture. Hamdioui et al [57] introduced CIM, a memristor based computation in memory architecture.…”

Section: Processing-in-resistive Memorymentioning

confidence: 99%

POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data

Kaplan

Yavits

Ginosar

2019

2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)

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Genome sequences contain hundreds of millions of DNA base pairs. Finding the degree of similarity between two genomes requires executing a compute-intensive dynamic programming algorithm, such as Smith-Waterman. Traditional von Neumann architectures have limited parallelism and cannot provide an efficient solution for large-scale genomic data. Approximate heuristic methods (e.g. BLAST) are commonly used. However, they are suboptimal and still compute-intensive.In this work, we present BioSEAL, a Biological SEquence ALignment accelerator. BioSEAL is a massively parallel non-von Neumann processing-inmemory architecture for large-scale DNA and protein sequence alignment. BioSEAL is based on resistive content addressable memory, capable of energyefficient and high-performance associative processing.We present an associative processing algorithm for entire database sequence alignment on BioSEAL and compare its performance and power consumption with state-of-art solutions. We show that BioSEAL can achieve up to 57× speedup and 156× better energy efficiency, compared with existing solutions for genome sequence alignment and protein sequence database search.

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“…[4,5] The nonvolatile latching characteristic of the memristor enables Boolean logic operations inside the memory. Because Borghetti et al first proposed the material implication (IMP) gate in a crossbar array in 2010, [6] various logic gates [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24] and their optimized cascading methods for realizing adders [25][26][27][28][29][30] have been demonstrated. They included two input gates, as well as multiple input gates, to perform more complicated gates efficiently.…”

mentioning

confidence: 99%

Stateful In‐Memory Logic System and Its Practical Implementation in a TaO_x‐Based Bipolar‐Type Memristive Crossbar Array

Kim

Son

Song

et al. 2020

Advanced Intelligent Systems

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Memristive stateful logic enables energy‐ and cost‐efficient in‐memory computing, which is desirable for edge computing in the coming Internet of Things (IoT) era. Researchers have recently developed various stateful logic gates and have shown viable computing applications based on ideal memristive characteristics. However, few studies have demonstrated a system‐level in‐memory computing operation that can address the practical issues affecting device realization. Herein, a practically viable stateful logic device based on a 1‐transistor−1‐memristor (1T1M) array structure is proposed, considering the inherently stochastic memristor characteristics. Details on how to select the viable stateful logic gates in a given memristor are shown, and as an example of logic cascading, they are implemented in a device to operate a multibit carry look‐ahead adder. Then, an in‐memory computing layout that can perform all of the computing functions—data storing, transferring, and executing—inside the memory, addressing data traffic issues, is suggested. Finally, a software/hardware mixed stateful logic emulator that can virtually mimic array‐level in‐memory computing hardware based on cell‐level memristive characteristics is demonstrated.

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Logic Design Within Memristive Memories Using Memristor-Aided loGIC (MAGIC)

Cited by 267 publications

References 48 publications

Fully Functional Logic‐In‐Memory Operations Based on a Reconfigurable Finite‐State Machine Using a Single Memristor

Fully Functional Logic‐In‐Memory Operations Based on a Reconfigurable Finite‐State Machine Using a Single Memristor

POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data

Stateful In‐Memory Logic System and Its Practical Implementation in a TaO_x‐Based Bipolar‐Type Memristive Crossbar Array

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Logic Design Within Memristive Memories Using Memristor-Aided loGIC (MAGIC)

Cited by 267 publications

References 48 publications

Fully Functional Logic‐In‐Memory Operations Based on a Reconfigurable Finite‐State Machine Using a Single Memristor

Fully Functional Logic‐In‐Memory Operations Based on a Reconfigurable Finite‐State Machine Using a Single Memristor

POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data

Stateful In‐Memory Logic System and Its Practical Implementation in a TaOx‐Based Bipolar‐Type Memristive Crossbar Array

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Stateful In‐Memory Logic System and Its Practical Implementation in a TaO_x‐Based Bipolar‐Type Memristive Crossbar Array