Logic Design of Digital Systems

Dietmeyer, D.L.

doi:10.1115/1.3426575

Cited by 62 publications

(41 citation statements)

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“…2. Note that using functional information, it may be possible to obtain a combinational model of a sequential circuit without balancing the circuit, such as in the case of switched balanced model [12], in which the circuit is balanced except for fanouts of known multiplexers, or sequential circuit with feedback loops [7], [14], [24].…”

Section: Circuit Subclasses and Atpg Methodsmentioning

confidence: 99%

Combinational automatic test pattern generation for acyclic sequential circuits

Kim

Agrawal

Saluja

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-It is known that the complexity of automatic test pattern generation (ATPG) for acyclic sequential circuits is similar to that of combinational ATPG. The general problem, however, requires time-frame expansion and multiple-fault detection and hence does not allow the use of available combinational ATPG programs. The first contribution of this work is a combinational single-fault ATPG method for the most general class of acyclic sequential circuits. Without inserting any real hardware, we create a functionally equivalent "balanced" ATPG model of the circuit in which all reconverging paths have the same sequential depth. Some primary inputs and gates are duplicated in this model, which is converted into a combinational circuit by shorting all flip-flops. A test vector obtained by a combinational ATPG program for a fault in this combinational circuit is transformed into a test sequence to detect a corresponding fault in the original sequential circuit. A combinational ATPG program finds tests for all but a small set of faults that must be explicitly detected as multiple-faults. Those are modeled for ATPG using the second contribution of this work, which is a generalized method to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most + 3 modeling gates for a fault of multiplicity . We show that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuck-at fault. Benchmark results show at least an order of magnitude saving in the ATPG CPU time by the new combinational method over sequential ATPG.Index Terms-Acyclic sequential circuit, automatic test pattern generation (ATPG), balanced model, combinational test generation, design for test (DFT), partial scan, test.

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Section: Circuit Subclasses and Atpg Methodsmentioning

confidence: 99%

Combinational automatic test pattern generation for acyclic sequential circuits

Kim

Agrawal

Saluja

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…These produce irredundant sum-of-products expressions (ISOPs) that are not necessarily minimum. For example, PRESTO [4], [33], MINI [15], ESPRESSO [3], and others [10], [24] produce nonminimum ISOPs.…”

Section: Introductionmentioning

confidence: 99%

Worst and best irredundant sum-of-products expressions

Sasao

Butler

2001

IEEE Trans. Comput.

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AbstractÐIn an irredundant sum-of-products expression (ISOP), each product is a prime implicant (PI) and no product can be deleted without changing the function. Among the ISOPs for some function f, a worst ISOP (WSOP) is an ISOP with the largest number of PIs and a minimum ISOP (MSOP) is one with the smallest number. We show a class of functions for which the Minato-Morreale ISOP algorithm produces WSOPs. Since the ratio of the size of the WSOP to the size of the MSOP is arbitrarily large when n, the number of variables, is unbounded, the Minato-Morreale algorithm can produce results that are very far from minimum. We present a class of multiple-output functions whose WSOP size is also much larger than its MSOP size. For a set of benchmark functions, we show the distribution of ISOPs to the number of PIs. Among this set are functions where the MSOPs have almost as many PIs as do the WSOPs. These functions are known to be easy to minimize. Also, there are benchmark functions where the fraction of ISOPs that are MSOPs is small and MSOPs have many fewer PIs than the WSOPs. Such functions are known to be hard to minimize. For one class of functions, we show that the fraction of ISOPs that are MSOPs approaches 0 as n approaches infinity, suggesting that such functions are hard to minimize.

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“…These and others studies were considered with more detail and generalized in [10,5]. Latter the operations of cube algebra was used for processor allocation in hypercube [6].…”

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confidence: 99%

Algebraic Approach to Transformations on Hypercube System

Kahramanli

Allahverdi

1996

MCA

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In this study some algebraic transformations on hypercube system are proposed. The presented transformations of forbidden subcubes provide defining set of all maximal and nonfaulty subcubes, and subset of minimal and nonfaulty subcubes included certain given vertices. It provides formal and simple findings of all the current sources and targets of information, and also the pathways between them. The correctness of all these transformations is proved by the aid of three theorems. In the proposed transformations there were three special operations of cube algebra applied, as subtraction, product and intersection on coordinates.Hypercube is a distributed parallel system consisting of 2 n identicalprocessors, each provided with its own sizable memory and interconnected with n neighbors. It has a homogeneous symmetric structure and has necessarily rich connectivity. It also has useful topology in which many other topologies, such as meshes, rings, trees and etc. can be embedded [13,2,3,6, 11, 15,1]. Hypercube multiprocessor systems usually have a large number of processors (nodes), so the probabilitythat some processor fails can be high. In order to prevent and determine the faulty nodes and links in the data communication there are many different kind of methods to reach the shortest paths between the source and the target nodes. For solving this problem it is applied traditional mathematical theory or heuristics, which can not completely take into account the peculiarities of the hypercube structure. These methods depend on the number of faulty components of hypercube and can not achieve necessary reliabilitywhen the number of faulty elements exceeds of cube dimension [2,3, 11, 15 ]. The last years for this purpose it

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Logic Design of Digital Systems

Cited by 62 publications

References 0 publications

Combinational automatic test pattern generation for acyclic sequential circuits

Combinational automatic test pattern generation for acyclic sequential circuits

Worst and best irredundant sum-of-products expressions

Algebraic Approach to Transformations on Hypercube System

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