Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation

Zhu, Qunxiong; Berger, Christian; Turner, Eric; Pileggi, Larry; Franchetti, Franz

doi:10.1007/s11265-012-0720-4

Cited by 3 publications

(6 citation statements)

References 15 publications

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“…Based on the same parallel access memory proposed in [7], a smart interpolation memory is proposed in [13] to accelerate the bottleneck of polar to rectangular grid conversion in Synthetic Aperture Radar application in an energy efficient way. The proposed interpolation memory is a LiM based seed table that uses a parallel access memory as a smaller seed table and interpolates the required data on the fly as if it is readily stored.…”

Section: Application-specific Smart-memoriesmentioning

confidence: 99%

“…The proposed interpolation memory is a LiM based seed table that uses a parallel access memory as a smaller seed table and interpolates the required data on the fly as if it is readily stored. Experimental simulation results in [13] show that an application specific LiM based architectures have great potential for improving the performance for such data-intensive applications.…”

Section: Application-specific Smart-memoriesmentioning

confidence: 99%

“…The energy and performance benefits of localizing computation for data-intensive applications are well known [2][3] [7][11] [13]. There are various examples of "processor-in-memory" designs wherein processing units are placed in memory abstraction [2] [3], or more recently, near data computing in 3D and 2.5D stacks to provide more bandwidth with less energy [11].…”

Section: Introductionmentioning

confidence: 99%

“…There are various examples of "processor-in-memory" designs wherein processing units are placed in memory abstraction [2] [3], or more recently, near data computing in 3D and 2.5D stacks to provide more bandwidth with less energy [11]. It has also been shown that various data intensive applications highly benefit from LiM blocks [12] [13]. However, there remains the need for physical synthesis (rather than compilation) of LiM blocks that are compatible with a full chip physical synthesis and offer the ability of system-level exploration.…”

Section: Introductionmentioning

confidence: 99%

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A synthesis methodology for application-specific logic-in-memory designs

Sumbul

Vaidyanathan

Zhu

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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For deeply scaled digital integrated systems, the power required for transporting data between memory and logic can exceed the power needed for computation, thereby limiting the efficacy of synthesizing logic and compiling memory independently. Logic-in-Memory (LiM) architectures address this challenge by embedding logic within the memory block to perform basic operations on data locally for specific functions. While custom smart memories have been successfully constructed for various applications, a fully automated LiM synthesis flow enables architectural exploration that has heretofore not been possible. In this paper we present a tool and design methodology for LiM physical synthesis that performs co-design of algorithms and architectures to explore system level trade-offs. The resulting layouts and timing models can be incorporated within any physical synthesis tool. Silicon results shown in this paper demonstrate a 250x performance improvement and 310x energy savings for a data-intensive application example.

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Section: Application-specific Smart-memoriesmentioning

confidence: 99%

Section: Application-specific Smart-memoriesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A synthesis methodology for application-specific logic-in-memory designs

Sumbul

Vaidyanathan

Zhu

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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“…For example, the AUX and CP arrays always access two consecutive entries simultaneously, the difference between which indicates the range of entries to check in their next data arrays (i.e., JC and IR). Therefore we implement them using our previous proposed parallel access memory, which allows to read out two adjacent SRAM entries in one clock cycle without too much overhead [28]. The JC array stores the non-zero column indices, and the access of which requires to search (access and compare) the data entries in a pre-determined range sequentially until the required column index is found.…”

Section: B Smart Cam-based Spgemm Lim Designmentioning

confidence: 99%

Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware

Zhu

Graf

Sumbul

et al. 2013

2013 IEEE High Performance Extreme Computing Conference (HPEC)

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Abstract-This paper introduces a 3D-stacked logic-in-memory (LiM) system to accelerate the processing of sparse matrix data that is held in a 3D DRAM system. We build a customized content addressable memory (CAM) hardware structure to exploit the inherent sparse data patterns and model the LiM based hardware accelerator layers that are stacked in between DRAM dies for the efficient sparse matrix operations. Through silicon vias (TSVs) are used to provide the required high inter-layer bandwidth. Furthermore, we adapt the algorithm and data structure to fully leverage the underlying hardware capabilities, and develop the necessary design framework to facilitate the design space evaluation and LiM hardware synthesis. Our simulation demonstrates more than two orders of magnitude of performance and energy efficiency improvements compared with the traditional multithreaded software implementation on modern processors.

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