Efficient and secure intellectual property (IP) design with split fabrication

Vaidyanathan, Kaushik; Liu, Renzhi; Sumbul, H. Ekin; Zhu, Qunxiong; Franchetti, Franz; Pileggi, Larry

doi:10.1109/hst.2014.6855561

Cited by 59 publications

(32 citation statements)

References 6 publications

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“…Therefore, only the information at the gate level of the circuit will be revealed to the untrusted companies. A similar method was achieved in detail for analog and digital IC circuits in [109]. The technique against recognition IC-based attacks has also been included, supported by experimental results, where an SRAM with a 1 KB size and a digital-to-analog converter with 14 bits have been used.…”

Section: Split Manufacturingmentioning

confidence: 79%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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Abstract:In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

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Section: Split Manufacturingmentioning

confidence: 79%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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“…With the capability of countering random mismatch with minimum analog circuits overhead involved, the SES method has been considered as a suitable analog circuit design methodology in sub-20 nm CMOS technology nodes [14]. The application of the SES method further extends to the area of trusted IC manufacturing using split fabrication, where analog circuit design intention can be obfuscated by redundant analog circuit components and associated digital control circuits [15].…”

Section: Extended Statistical Element Selection (Eses)mentioning

confidence: 99%

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

2016

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“…Furthermore, the recognition attack mechanism used in [12] cannot accurately explain the issue with RF split fabrication. To better guide the implementation of split manufacturing in RF circuits and to balance between the security level and design efforts, we propose three approaches/scenarios to perform the RF split fabrication:…”

Section: Split Manufacturing In Rf Circuitsmentioning

confidence: 99%

“…More recently, Vaidyanathan et al investigated the feasibility of split fabrication after the metal1 layer, so that untrusted foundries only have the information of basic gate-level blocks [11]. A similar technique is then applied to digital/analog IP designs [12]. A defense strategy against recognition attacks on IPs and an obfuscation method were both proposed, as well as experimental demonstrations on a 1-KB SRAM and a 14-bit current steering digital-to-analog converter (DAC).Jagasivamani et al examined several front-end obfuscation techniques, information theory metrics and impacts on performance penalties [13].…”

Section: Split Manufacturing In the Digital Domainmentioning

confidence: 99%

“…Even though the concept is straightforward, a successful implementation requires further research on various aspects, especially the balance between cost and security when the designer splits the layout into FEOL and BEOL. Analytical and experimental results have already been presented for digital circuits [8][9][10][11][12][13][14][15]. However, the analog/RF designs are rarely discussed when using split manufacturing, even though analog/RF circuits are more likely to be IP piracy victims than their digital counterparts.…”

Section: Introductionmentioning

confidence: 99%

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Beyond the Interconnections: Split Manufacturing in RF Designs

Yuan

Jin

2015

Electronics

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With the globalization of the integrated circuit (IC) design flow of chip fabrication, intellectual property (IP) piracy is becoming the main security threat. While most of the protection methods are dedicated for digital circuits, we are trying to protect radio-frequency (RF) designs. For the first time, we applied the split manufacturing method in RF circuit protection. Three different implementation cases are introduced for security and design overhead tradeoffs, i.e., the removal of the top metal layer, the removal of the top two metal layers and the design obfuscation dedicated to RF circuits. We also developed a quantitative security evaluation method to measure the protection level of RF designs under split manufacturing. Finally, a simple Class AB power amplifier and a more sophisticated Class E power amplifier are used for the demonstration through which we prove that: (1) the removal of top metal layer or the top two metal layers can provide high-level protection for RF circuits with a lower request to domestic foundries; (2) the design obfuscation method provides the highest level of circuit protection, though at the cost of design overhead; and (3) split manufacturing may be more suitable for RF designs than for digital circuits, and it can effectively reduce IP piracy in untrusted off-shore foundries.

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Efficient and secure intellectual property (IP) design with split fabrication

Cited by 59 publications

References 6 publications

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

Beyond the Interconnections: Split Manufacturing in RF Designs

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