Load and store reuse using register file contents

Önder, Soner; Gupta, Rajiv

doi:10.1145/377792.377850

Cited by 31 publications

(40 citation statements)

References 18 publications

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“…Speculative memory bypassing (SMB) [10,11,13,14,25] optimizes in-window memory communication. SMB "short-circuits" the store-load pair in a DEF-storeload-USE chain by directly connecting the DEF to the USE using the register map table.…”

Section: Speculative Memory Bypassing (Smb)mentioning

confidence: 99%

“…SMB "short-circuits" the store-load pair in a DEF-storeload-USE chain by directly connecting the DEF to the USE using the register map table. Initial proposals used SMB only for its store-load communication latency reduction benefits; bypassed loads still executed in the out-of-order engine for verification [10,11,25]. Subsequent proposals used SMB to amplify execution core bandwidth and capacity as well, by allowing bypassed loads to skip the out-of-order engine and using in-order load re-execution for verification [13,14].…”

Section: Speculative Memory Bypassing (Smb)mentioning

confidence: 99%

“…The NoSQ microarchitecture uses speculative memory bypassing (SMB) [10,11,13,14,25] as a replacement for conventional store-queue based forwarding. SMB is a previously-proposed technique that dynamically transforms in-window store-load communication into register communication.…”

Section: Introductionmentioning

confidence: 99%

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NoSQ: Store-Load Communication without a Store Queue

2007

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This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the out-of-order engine. NoSQ implements store-load communication using speculative memory bypassing (SMB), the dynamic shortcircuiting of DEF-store-load-USE chains to DEF-USE chains. Whereas previous proposals used SMB as an opportunistic complement to conventional store queue-based forwarding, NoSQ uses SMB as a store queue replacement.NoSQ relies on two supporting mechanisms. The first is an advanced store-load bypassing predictor that for a given dynamic load can predict whether that load will bypass and the identity of the communicating store. The second is an efficient verification mechanism for both bypassed and non-bypassed loads using in-order load re-execution with an SMB-aware store vulnerability window (SVW) filter.The primary benefit of NoSQ is a simple, fast datapath that does not contain store-load forwarding hardware; all loads get their values either from the data cache or from the register file. Experiments show that this simpler design -despite being more speculative -slightly outperforms a conventional store-queue based design on most benchmarks (by 2% on average). Microarchitecture, 2006, MICRO-39, pages 285-296. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Comments Copyright 2006 IEEE. Reprinted from Proceedings of the 39th Annual IEEE/ACM International Symposium on

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Section: Speculative Memory Bypassing (Smb)mentioning

confidence: 99%

Section: Speculative Memory Bypassing (Smb)mentioning

confidence: 99%

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NoSQ: Store-Load Communication without a Store Queue

2007

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“…One approach to implement load and store reuse is to manage registers as a level in the memory hierarchy [24]. Another approach uses instruction reuse to exploit both same instruction and different instruction redundancy [23].…”

Section: Figure 9 Comparison To Instruction Reuse and Value Predictionmentioning

confidence: 99%

A Speculative Trace Reuse Architecture with Reduced Hardware Requirements

Pilla

Childers

Costa

et al. 2006

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06)

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“…One approach to implement load and store reuse is to manage registers as a level in the memory hierarchy [29]. Another approach uses instruction reuse to exploit both same instruction and different instruction redundancy [28].…”

Section: Previous Workmentioning

confidence: 99%