Lithography-Aware Physical Design

Pan, David Z.

doi:10.1109/icasic.2005.1611242

Cited by 6 publications

(3 citation statements)

References 16 publications

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“…resolution assist feature (SRAF, also called scattering bar), off-axis illumination (OAI), double-patterning technology (DPT), etc. They can effectively achieve better lithographic printability, but their costs are usually high [28]. For example, OPC may generate a great number of polygons on a mask, while DPT needs to use two complementary masks on a target wafer, both resulting in very high mask costs.…”

Section: Originalmentioning

confidence: 99%

Recent research development in physical design for manufacturability

Chen

Lai

et al. 2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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As IC process geometries scale down to the nanometer era, the industry faces severe challenges of manufacturing limitations. For the imperfect manufacturing process, physical design for manufacturability has played an essential role in resolution and thus yield enhancement to guarantee yield. In this paper, we introduce three major challenges arising from the nanometer process technology and survey major existing techniques for handling the challenges in physical design for manufacturability.

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Section: Originalmentioning

confidence: 99%

Recent research development in physical design for manufacturability

Chen

Lai

et al. 2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…RETs are expensive both in terms of design volume (upto 10x increase) and mask cost and full chip OPC simulations can take hundreds of hours [7]. The author stresses on the importance of modeling and feeding lithographic metrics upstream, to bridge the gap between design and manufacturing.…”

Section: Introductionmentioning

confidence: 99%

Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability

Dhumane

Srivathsa

Kundu

2011

2011 IEEE Computer Society Annual Symposium on VLSI

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Technology scaling has brought about sub-wavelength lithography. Sub-wavelength lithography requires resolution enhancement techniques (RETs) including significant layout constraints and manufacturability verification using lithography simulation. Despite the use of these techniques, the design iterations may take too long and may not converge. In standard cell based designs, inter-feature interactions across abutting standard cells can result in reduced design and parametric yield. In this paper, we propose a litho aware design methodology that aims at fixing the violations due to standard cell abutments. The major contributions of this work are a phased approach towards elimination of lithography violations by 1) Pre-characterization of abutments for early detection of violations, 2) Iterative changes to placement to minimize violations and 3) SRAF insertion rules to eliminate violations. Experimental results on ISCAS and AES benchmark circuits show that the proposed methodology eliminates all lithography violations with no impact on area and minimal impact on performance.

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“…These techniques include optical proximity correction (OPC), sub-resolution assist feature (SRAF, also called scattering bar), phase-shifting mask (PSM), off-axis illumination (OAI), etc. They can effectively achieve better lithographic printability, but their costs are usually high [30]. For example, OPC may generate a great number of polygons on a mask, while PSM need to use phase shifters at the mask level, both resulting in very high mask costs.…”

Section: Introductionmentioning

confidence: 99%

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability

Lin

Tsai

Lee

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical design for manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this paper, we introduce major challenges arising from nanometer process technology, survey key existing techniques for handling the challenges, and provide some future research directions in physical design for manufacturability and reliability.

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Lithography-Aware Physical Design

Cited by 6 publications

References 16 publications

Recent research development in physical design for manufacturability

Recent research development in physical design for manufacturability

Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability

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