Liquid source chemical vapor deposition of high-dielectric-constant (Ba, Sr)TiO3 films

Abstract

High‐dielectric‐constant (Ba, Sr)TiO3 [BST] films were deposited by the liquid source chemical vapor deposition (CVD) method. The system consisted of a single‐wafer, low‐pressure thermal CVD reactor, a vaporizer for liquid source materials, and a shower‐type gas nozzle head, giving stable BST film deposition on a 6‐in. diam. substrate with uniform thickness and uniform chemical composition ratio. The source materials employed were Ba(DPM)2, Sr(DPM)2, and TiO(DPM)2 dissolved in tetrahydrofuran (THF), resulting in conformal step coverage of BST films at lowered substrate temperatures, where DPM denotes dipivaloylmethanate. Moreover, the two‐step deposition technique was developed to restart protrusions formed on BST film surfaces at low temperatures, where the BST films consisted of a buffer layer and a main layer; the buffer layer was a layer about 60 Å thick of CVD‐BST film annealed in N2. Thus, the two‐step CVD deposition of BST films on Pt and Ru electrodes achieved an equivalent SiO2 thickness of teq ∼ 0.5 nm, a leakage current of JL ∼ 1.0 × 10−8 A/cm2 (at +1.1 V), and a dielectric loss of tan δ ∼ 0.01 at a total film thickness of 250 Å, along with conformal coverage of 80% for a trench with an aspect ratio of 0.65. Then, for BST films deposited on patterned electrodes 0.24 μm wide, 0.60 μm deep, and 0.15 μm high (each spaced by 0.14 μm), the capacitance was demonstrated to be increased without significant deterioration of the leakage current: the capacitance was increased in comparison with that for films on flat electrodes, by a factor corresponding to the increase in surface area due to sidewalls of storage‐node‐like pattern features. This capacitance increase reflects the most characteristic advantage of CVD, an excellent step coverage on microscopic pattern features. These electrical properties satisfy the specifications for capacitors for Gb‐scale dynamic random access memories (DRAMs), giving a storage capacitance of more than 25 fF/cell for a stacked capacitor having a storage node 0.2 to 0.3 μm high. © 1998 Scripta Technica, Electr Eng Jpn, 125(1): 47–54, 1998