Link Testing: a Survey of Current Trends in Network on Chip

Aghaei, Babak; Khademzadeh, Ahmad; Reshadi, Midia; Badie, Kambiz

doi:10.1007/s10836-017-5646-0

Cited by 11 publications

(4 citation statements)

References 96 publications

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“…Several survey papers were published, covering many aspects of NoC research, ranging from application mapping [1]- [3], topology design and routing algorithms [4], [18], [24], [25], fault tolerant NoC [5], optical NoC [6], [7], low power design [8], [9], NoC for QoS [10], [11], testing [12], simulators [13], to reconfigurable network [14], etc. However, all these survey papers are based on the domain knowledge of the human experts (authors).…”

Section: Related Work a Survey Papers In The Noc Areamentioning

confidence: 99%

“…Over the past twenty years, a number of good survey papers covering one or a few specific aspects of NoC, including application mapping [1]- [3], to topology design and routing algorithms [4], to fault tolerant NoC [5], to optical NoC [6], [7], to low power design [8], [9], NoC for QoS [10], [11], testing [12], simulators [13], and reconfigurable network [14], and many others, have been published. Since these survey papers only focus on specific research subjects/topics, by human experts and based on the authors' own knowledge of the subjects, these surveys did not provide an overarching and objective view of the NoC, and the surveys did not quite follow a data-driven analysis method to quantify the dynamics of NoC research and make a sound prediction of what is lying ahead.…”

Section: Introductionmentioning

confidence: 99%

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Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective

Wang²,

Sun

et al. 2021

IEEE Access

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The academia and industry have been pursuing network-on-chip (NoC) related research since two decades ago when there was an urgency to respond to the scaling and technological challenges imposed on intra-chip communication in SoC designs. Like any other research topic, NoC inevitably goes through its life cycle: A. it started up (2000)(2001)(2002)(2003)(2004)(2005)(2006)(2007) and quickly gained traction in its own right; B. it then entered the phase of growth and shakeout (2008)(2009)(2010)(2011)(2012)(2013) with the research outcomes peaked in 2010 and remained high for another four/five years; C. NoC research was considered mature and stable (2014-2020), with signs showing a steady slowdown. Although from time to time, excellent survey articles on different subjects/aspects of NoC appeared in the open literature, yet there is no general consensus on where we are in this NoC roadmap and where we are heading, largely due to lack of an overarching methodology and tool to assess and quantify the research outcomes and evolution. In this paper, we address this issue from the perspective of three specific complex networks, namely the citation network, the subject citation network, and the co-authorship network. The network structure parameters (e.g., modularity, diameter, etc.) and graph dynamics of the three networks are extracted and analyzed, which helps reveal and explain the reasons and the driving forces behind all the changes observed in NoC research over 20 years. Additional analyses are performed in this study to link interesting phenomena surrounding the NoC area. They include:(1) relationships between communities in citation networks and NoC subjects, (2) measure and visualization of a subject's influence score and its evolution, (3) knowledge flow among the six most popular NoC subjects and their relationships, (4) evolution of various subjects in terms of number of publications, (5) collaboration patterns and cross-community collaboration among the authors in NoC research, (6) interesting observation of career lifetime and productivity among NoC researchers, and finally (7) investigation of whether or not new authors are chasing hot subjects in NoC. All these analyses have led to a prediction of publications, subjects, and co-authorship in NoC research in the near future, which is also presented in the paper.

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Section: Related Work a Survey Papers In The Noc Areamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective

Wang²,

Sun

et al. 2021

IEEE Access

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“…The reliability of the system has grown into a major challenge in NoC design [123]. Various research works have discussed the issue of reliability in NoC, addressed multiple problems and factors causing reliability issues and proposed faulttolerant models and frameworks to detect and diagnose faults [124]- [126]. Work presented in [123] categorizes reliability into fault avoidance and fault tolerance.…”

Section: Fault Tolerance Application Mapping In Nocmentioning

confidence: 99%

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

et al. 2020

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Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the highperformance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip. I. INTRODUCTION System-on-Chip (SoC) is an archetype for the design and implementation of on-chip circuits that can support multiple systems on a single chip. The ever-rising number of processing cores on a single chip has made the efficiency of onchip designs as one of the major aspects in evaluating the average performance of embedded SoC. To fulfill the performance needs and to provide flexibility in the designs the field of Network on Chip (NoC) has emerged that separates the communication from the computation. Many surveys [1]-[7] are published in general and textbooks are also available on the topic [8]-[10]. There is still a need to solve more advanced research problems in NoC. Application mapping on NoC architecture has a prominent place among all the research problems which can be arbitrated from the published The associate editor coordinating the review of this manuscript and approving it for publication was Eyuphan Bulut. papers and current trends. This survey assumes a textbooklevel acquaintance of NoC terminology. The aim is to provide a comprehensive overview of all the aspects of application mapping (task graph generation, scheduling, optimization techniques, simulation setup, and performance evaluation metrics). The organization of this survey is as follows; first, we provide the reader the need and overview of application mapping in NoC presented in Section I. A detailed review and calcification of application mapping techniques in NoCs are discussed in Section II. The current and latest trends in application mapping are summarized in Section III. In Section IV performance comparison and the points that can create the difference between these techniques are highlighted. Finally, Section VI concludes this paper. A. MOTIVATION AND SCOPE Mostly synthetic traffic patterns are used to imitate the functionalities of rea...

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“…N ETWORK-ON-CHIP, (NoC) the emerging technology has become popular in interconnecting multiple cores on a chip [1]. Multi-core processors use NoC to interconnect thousands of cores rather than shared buses or point-to-point interconnect wires [2]. Switch Allocation (SA) is used to assign output ports to input ports [3].…”

Section: Introductionmentioning

confidence: 99%

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

2021

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Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally used Input-Queued Routers (IQR), packets are arranged in a particular order in each Virtual Channel (VC). This implementation is vulnerable to HoL blocking, as the switch allocator can allocate only those packets which are available at the head in a VC. In this paper, Swapped Buffer (SB) Router architecture is proposed to schedule packets in input buffers by using SB registers. The VCs are designed as SBs, this allows the packets stored in SB registers along with the head packet of VC to participate in SA. The concept of the SB register minimizes the conflicts in SA and thus reduces HoL blocking, therefore improves the performance of NoC. This paper proposes a priority mechanism to prioritize the non-head packets as compared to head packets in case of conflict between them. Two methods have been proposed in this paper, to enhance the performance of the NoC router. First, a VC allocation technique is proposed to optimize the order of packets in the input buffer. Next, SB-Router is combined with the Fill VC allocation technique to further enhance the performance of NoC routers. The performance of the proposed router is evaluated and the experimental results indicate that our design achieves latency improvement of 68.75% over (Time-Series) TS-Router for uniform traffic at the injection rate of 0.42 flits/cycle for a 64 node mesh network with moderate power consumption and area usage. The performance improvement in packet latency for traces from Princeton Application Repository for Shared-Memory Computers (PARSEC) has also been evaluated. With the achieved reduction in latency, the proposed method has the potential to serve high-speed operations while mapping different applications on multiple core architectures.

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Link Testing: a Survey of Current Trends in Network on Chip

Cited by 11 publications

References 96 publications

Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective

Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

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