Lightweight True Random Bit Generators in PLDs: Figures of Merit and Performance Comparison

Addabbo, Tommaso; Fort, Ada; Moretti, Riccardo; Mugnaini, Marco; García-Bosque, M.

doi:10.1109/iscas.2019.8702791

Cited by 13 publications

(16 citation statements)

References 17 publications

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“…Furthermore, even using the same feedback polynomial, it has been recently proven that, depending on the location within the FPGA where the system is implemented, the behavior of the system can change drastically, sometimes resulting in poor random sequences [23], [24].…”

Section: Issues Of Firo and Garo Trngsmentioning

confidence: 99%

Proposal and Analysis of a Novel Class of PUFs Based on Galois Ring Oscillators

et al. 2020

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In this paper, the possibility of using Galois ring oscillators to construct physically unclonable functions (PUFs) has been studied. The idea is to use novel PUF architectures, similar as the ring oscillator PUFs that, instead of comparing frequencies, compare the statistical bias of pairs of oscillators implemented in different locations. To study the viability of these systems, three different Galois oscillators have been implemented in several locations in several FPGAs and we have studied the main properties of their bias: repeatability, variability with the location, variability with the FPGA and spatial autocorrelation. Based on this study, we have determined that the bias of these oscillators meet the requirements that are needed to be used to construct a PUF. Finally, a PUF based on comparing the bias of neighboring 7-LUT Galois ring oscillators have been implemented and analyzed. The experimental results show that this PUF generates uniform responses that are highly reproducible and unique, making this PUF suitable for being used in identification applications. INDEX TERMS Fibonnaci ring oscillators, FPGA, Galois ring oscillators, hardware security, physically unclonable function, ring oscillator. Identificability Random variations due to manufacturing process Physical unclonability PUF Challenges Responses • Easy implementation • Low-power consumption • "Volatile secret"

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Section: Issues Of Firo and Garo Trngsmentioning

confidence: 99%

Proposal and Analysis of a Novel Class of PUFs Based on Galois Ring Oscillators

et al. 2020

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“…The well know Ring Oscillator circuit, a loop of an odd number of inverting logic gates, is among the simplest examples of a DNO. Other systems classifiable as DNOs have been presented in [14], [19]- [21].…”

Section: Digital Nonlinear Oscillatorsmentioning

confidence: 99%

“…Bringing together PLD design, circuit modeling and the analysis of nonlinear dynamical systems, a first investigation of different DNO architectures have been presented in [19], [21], [22]. The authors showed that, depending on both the network topology and the hardware implementation, DNOs can exhibit complex dynamical behavior.…”

Section: Digital Nonlinear Oscillatorsmentioning

confidence: 99%

“…2 includes two xor gates, one negated xor (nxor) gate and three active delay nodes (del) resulting, e.g., from routing elements in PLDs (connection and switch boxes) [22]. A special symbol for the delay nodes has been introduced to remark that they are digital rectifying delay gates [19], [21], [22].…”

Section: A a Novel Dno Sub-circuit Topology Compatible With Complex mentioning

confidence: 99%

“…The DNO in Fig. 14 has been first compared with two other DNOs, namely a 7-nodes Ring Oscillator (DNO A) and a 7-nodes Golíc Galois Ring Oscillator (DNO B) [19], [21], by means of the measurement campaign hereafter discussed. We have chosen these solutions for the comparison because of the following reasons: 1) they involve a similar hardware complexity; 2) they exhibit stable simple and complex periodic dynamics, respectively; 3) in both of them the chief information generation mechanism has been shown to be due to phase noise and jitter caused by electronic noise.…”

Section: B Experiments: Raw Entropy Source Low-level Characterizationmentioning

confidence: 99%

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A New Class of Digital Circuits for the Design of Entropy Sources in Programmable Logic

Addabbo

Fort

Moretti

et al. 2020

IEEE Trans. Circuits Syst. I

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We propose a novel class of Digital Nonlinear Oscillators (DNOs) supporting complex dynamics, including chaos, suitable for the definition of high-performance and low-complexity entropy sources in Programmable Logic Devices (PLDs). We derive our proposal from the analysis of simplified models, investigated as non-autonomous nonlinear dynamical systems under different excitation conditions. The study lead the authors to the design of a fully digital entropy source consuming only two slices of a Xilinx FPGA, including post-processing, sufficient to define a class of TRNGs capable to pass the NIST standard tests for randomness in any worst case experimentally tested by the authors (6 chips, 96 generators). The solution has been compared with others published in the literature, confirming the validity of the proposal.

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