A New Class of Digital Circuits for the Design of Entropy Sources in Programmable Logic

Addabbo, Tommaso; Fort, Ada; Moretti, Riccardo; Mugnaini, Marco; Takaloo, Hadis; Vignoli, Valerio

doi:10.1109/tcsi.2020.2977920

Cited by 17 publications

(4 citation statements)

References 36 publications

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“…We have evaluated the capability of the proposed algorithm to select the best source among a set of sixteen based on 7-nodes Galois Ring Oscillators [30], [33], [36], [37], implemented in a Xilinx Artix 7 xc7a35 FPGA. The entropy of such Digital Nonlinear Oscillators (DNOs) is sensitive to the variability of the delays introduced by the FPGA routing circuitry in the feedback loops [30], [33], [37], and the 16 entropy sources were deliberately obtained varying the routing paths. The nonlinear dynamical systems were digitized (1bit digitization) according to a sampling frequency of 100MHz, as discussed in [30], [33], and [37].…”

Section: B Experiments: Application To Fpga Digital Nonlinear Oscilla...mentioning

confidence: 99%

“…The entropy of such Digital Nonlinear Oscillators (DNOs) is sensitive to the variability of the delays introduced by the FPGA routing circuitry in the feedback loops [30], [33], [37], and the 16 entropy sources were deliberately obtained varying the routing paths. The nonlinear dynamical systems were digitized (1bit digitization) according to a sampling frequency of 100MHz, as discussed in [30], [33], and [37].…”

Section: B Experiments: Application To Fpga Digital Nonlinear Oscilla...mentioning

confidence: 99%

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A Stochastic Algorithm to Design Min-Entropy Tuning Controllers for True Random Number Generators

Addabbo

Fort

Moretti

et al. 2022

IEEE Trans. Circuits Syst. I

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We discuss a stochastic algorithm to design tuning controllers for cryptographic True Random Number Generators, compliant to NIST recommendations, as an effective low-complexity solution to counteract entropy variability in integrated architectures implementing tunable entropy sources. Taking as a reference the min-entropy concept, we discussed the proposal from both the theoretical and hardware design points of view, validating claims with proofs and experiments. Depending on the target accuracy, the proposed architecture is scalable, and its profitable use in TRNG design strongly depends on the kind of core entropy sources taken into account. Furthermore, we show that the low-complexity entropy measurement techniques exploited in this proposal can be used to design a legitimate alternative to the Adaptive Proportion Health Test recommended in the NIST 800.90B publication.

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Section: B Experiments: Application To Fpga Digital Nonlinear Oscilla...mentioning

confidence: 99%

Section: B Experiments: Application To Fpga Digital Nonlinear Oscilla...mentioning

confidence: 99%

A Stochastic Algorithm to Design Min-Entropy Tuning Controllers for True Random Number Generators

Addabbo

Fort

Moretti

et al. 2022

IEEE Trans. Circuits Syst. I

Self Cite

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“…In [23], the analog transfer function for an LUT6 instance used as a two-input xor gate is modeled as:…”

Section: A Numerical Analysismentioning

confidence: 99%

A Dual Entropy-Based Digital Random Number Generator

Ozturk¹,

Ergün

2021

IEEE Access

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This paper introduces the dual-entropy method for oscillator-based digital random number generators (RNG). The standard model for elaborating jitter-based RNG is expanded to account for the sampling time uncertainty. It is explained that combining the jitter of the sampling clock with the uncertainty of the sampled signal proves to be the most efficient method for harvesting entropy from jitter. Dual-entropy configuration also improves the robustness of the RNG against correlation, interference, and injection-based attacks in hardware. Numerical analysis and experimental results show that the negative effect of external interference on the entropy of the output bitstream is significantly reduced in dual-entropy-based RNG. The proposed method is demonstrated on a ring-oscillator-based design and implemented on FPGA. It is tested using NIST 800-22, Dieharder, and TestU01 batteries and observed to produce successful random bitstreams at a maximum center frequency of 45 MHz on Zedboard Zynq and 114 MHz on ZCU102 Zynq Ultrascale+ evaluation kits without post-processing.

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“…Compared with the analog circuit, the accuracy of components in digital circuit is less affected by the environment, and the repeatability and flexibility are superior to analog circuit. Most of the existing studies use high-performance chips such as field programmable gate array (FPGA) or digital signal processor (DSP) to generate chaos (Addabbo et al , 2020; He et al , 2018; Koyuncu et al , 2020; Tuna et al , 2019; Xiao et al , 2019), but a few use MCU to realize chaos and apply it to secure communication. MCU has the advantages of high economic benefit and wide application compared with FPGA and DSP.…”

Section: Introductionmentioning

confidence: 99%

Design of a fractional-order chaotic secure communication circuit based on sliding mode theory and microcontroller

Zhou

Wang

et al. 2022

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Purpose With the development of integrated circuit and communication technology, digital secure communication has become a research hotspot. This paper aims to design a five-dimensional fractional-order chaotic secure communication circuit with sliding mode synchronous based on microcontroller (MCU). Design/methodology/approach First, a five-dimensional fractional-order chaotic system for encryption is constructed. The approximate numerical solution of fractional-order chaotic system is calculated by Adomian decomposition method, and the phase diagram is obtained. Then, combined with the complexity and 0–1 test algorithm, the parameters of fractional-order chaotic system for encryption are selected. In addition, a sliding mode controller based on the new reaching law is constructed, and its stability is proved. The chaotic system can be synchronized in a short time by using sliding mode control synchronization. Findings The electronic circuit is implemented to verify the feasibility and effectiveness of the designed scheme. Originality/value It is feasible to realize fractional-order chaotic secure communication using MCU, and further reducing the synchronization error is the focus of future work.

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A New Class of Digital Circuits for the Design of Entropy Sources in Programmable Logic

Cited by 17 publications

References 36 publications

A Stochastic Algorithm to Design Min-Entropy Tuning Controllers for True Random Number Generators

A Stochastic Algorithm to Design Min-Entropy Tuning Controllers for True Random Number Generators

A Dual Entropy-Based Digital Random Number Generator

Design of a fractional-order chaotic secure communication circuit based on sliding mode theory and microcontroller

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