Lifetime-sensitive modulo scheduling in a production environment

Llosa, Josep; Ayguadé, Eduard; González, Antonio; Valero, Mateo; Eckhardt, Jason

doi:10.1109/12.910814

Cited by 50 publications

(24 citation statements)

References 33 publications

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“…Integrated register-sensitive iterative software pipelining (IRIS) [34] modifies the IMS technique to minimize register requirements. Swing modulo scheduling (SMS) [35,36] does not use backtracking but orders graph nodes guarantying effective schedules with low register pressure. The modulo scheduling with integrated register spilling (MIRS) in [37] suggests to integrate the possibility of storing data temporally out to memory (using spill code) when a schedule aims to exceed the number of available registers in the processor.…”

Section: Background On the Modulo Schedulingmentioning

confidence: 99%

“…One of the most efficient scheduling heuristic is SMS as evaluated in [32,35,36]. Applying SMS on our FFT problem in the TI C66 core, it produced a schedule of II = MII with a minimum register usage of 20 per core side (40 needed registers), which is greater than the available registers for the DAG allocation, meaning that this is not an implementable schedule.…”

Section: Introductionmentioning

confidence: 99%

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Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Bahtat

Belkouch

Elleaume

et al. 2016

EURASIP J. Adv. Signal Process.

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The fast Fourier transform (FFT) is perhaps today's most ubiquitous algorithm used with digital data; hence, it is still being studied extensively. Besides the benefit of reducing the arithmetic count in the FFT algorithm, memory references and scheme's projection on processor's architecture are critical for a fast and efficient implementation. One of the main bottlenecks is in the long latency memory accesses to butterflies' legs and in the redundant references to twiddle factors. In this paper, we describe a new FFT implementation on high-end very long instruction word (VLIW) digital signal processors (DSP), which presents improved performance in terms of clock cycles due to the resulting low-level resource balance and to the reduced memory accesses of twiddle factors. The method introduces a tradeoff parameter between accuracy and speed. Additionally, we suggest a cache-efficient implementation methodology for the FFT, dependently on the provided VLIW hardware resources and cache structure. Experimental results on a TI VLIW DSP show that our method reduces the number of clock cycles by an average of 51 % (2 times acceleration) when compared to the most assembly-optimized and vendor-tuned FFT libraries. The FFT was generated using an instruction-level scheduling heuristic. It is a modulo-based register-sensitive scheduling algorithm, which is able to compute an aggressively efficient sequence of VLIW instructions for the FFT, maximizing the parallelism rate and minimizing clock cycles and register usage.

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Section: Background On the Modulo Schedulingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Bahtat

Belkouch

Elleaume

et al. 2016

EURASIP J. Adv. Signal Process.

View full text Add to dashboard Cite

show abstract

“…However, such algorithms usually assume a fixed set of resource constraints [16]- [20], while time-constrained variations [21] are much less frequently used. This is especially true when concerning scheduling for VLIW processors, where scheduling and partitioning are only considered after the hardware has been determined.…”

Section: Previous Research On Parallelism Estimationmentioning

confidence: 99%

Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors

Jordans

Corvino

Jóźwiak

2012

2012 15th Euromicro Conference on Digital System Design

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Abstract-Customization of a (generic) processor to a particular application makes it possible to achieve high performance within a tight energy budget. Most of the published research works on processor customization extend a simple base processor with custom instructions. Only few works have considered a full instruction-set customization for complex highly parallel Very Long Instruction Word (VLIW) architectures. This paper discusses the parallelism estimation for a full instruction-set synthesis for VLIW processors and evaluates four methods to compute the maximum parallelism of a given application. We explain important reasons for computing and using such parallelism bounds, discuss the implementation of several methods, and our experimental research performed to evaluate the efficiency of each method.

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“…After computation, this range is scanned and the corresponding instruction heuristically placed either as early or as late as possible, depending on the already scheduled nodes and for the preference of short register lifetimes. Another approach, known as swing scheduling, is presented by Llosa et al as part of a production compiler [15]. The proposed solution adapts an iterative scheme and, similar to slack scheduling, also uses precomputed parameters, such as valid placement slots and mobility values, to assist in scheduling.…”

Section: Introductionmentioning

confidence: 99%

Integrated modulo scheduling and cluster assignment for TI TMS320C64x+ architecture

Kim

Krall

2014

Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems

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For the exploitation of the available parallelism clustered Very Long Instruction Word (VLIW) processors rely on highly optimizing compilers. Aiming this parallelism, many advanced compiler concepts have been developed and proposed in the past. Many of them concentrate on loops only as most of the execution time is usually spent executing repeating patterns of code. Software pipelining techniques, such as modulo scheduling, try to speed up the execution of loops by simultaneous initiation of multiple iterations, thus additionally exploiting parallelism across loop iteration boundaries. This increases processor utilization at the cost of higher complexity which is especially true for architectures featuring multiple clusters and distributed register files. Additional scheduling constraints need to be considered in order to produce valid schedules. Targeting TI's TMS320C64x+ clustered VLIW architecture, we describe a code generation approach that adapts an iterative modulo scheduling scheme, and also propose two heuristics for cluster assignment, all together implemented within the popular LLVM compiler framework. We cover implementation of developed algorithms, present evaluation results for a selection of benchmarks popular for embedded system development and discuss gained insights on the topics of integrated modulo scheduling and cluster assignment in this paper.

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Lifetime-sensitive modulo scheduling in a production environment

Cited by 50 publications

References 33 publications

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors

Integrated modulo scheduling and cluster assignment for TI TMS320C64x+ architecture

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