Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors

Jordans, Roel; Corvino, Rosilde; Jóźwiak, L.

doi:10.1109/dsd.2012.21

“…They include results related to such important problems as energy consumption management, application analysis and restructuring or actual automatic coherent SW and HW co-development. More information on the research results from ASAM can be found in several already published papers with links to them at the ASAM home-page (http://www.asam-project.org/), a few more specific papers in this conference [27][28][29], [31], [32], and several papers under preparation that will be published soon.…”

Section: Discussionmentioning

confidence: 99%

ASAM: Automatic architecture synthesis and application mapping

Jóźwiak

¹

,

Lindwer²,

Corvino

³

et al. 2013

Microprocessors and Microsystems

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• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Download date: 13. May. 2018 1  Abstract -This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable applicationspecific instruction-set processors (ASIPs). It presents an overview of the research being currently performed in the scope of the European project ASAM (Architecture Synthesis and Application Mapping) of the ARTEMIS program. The paper briefly presents the results of our analysis of the main problems to be solved and challenges to be faced in the design of such heterogeneous MPSoCs. It explains which system, design, and electronic design automation (EDA) concepts seem to be adequate to resolve the problems and address the challenges. Finally, it introduces and briefly discusses the design-flow and its main stages proposed by the ASAM project consortium to enable an effective and efficient solution of these problems.Index Terms-embedded systems, heterogeneous multiprocessor system-on-chip (MPSoC), customizable ASIPs, architecture synthesis, MPSoC and ASIP design automation;

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“…More extreme cases, resulting in larger overestimations, can be constructed in a similar fashion. 3) Maximum parallelism: The maximum parallelism [21], [22] can be estimated in a way that is similar to the estimation of the force based parallelism. The only difference is that all nodes are counted with the same weight and that the length of the schedule interval is not taken into account as shown in figure 4.…”

Section: ) Average Parallelismmentioning

confidence: 99%

“…3) Maximum parallelism (MP) [20]- [22], estimated by finding the maximal number of operations which can be scheduled in parallel. 4) Required parallelism (RP) [17], [21], [22], estimating the minimal upper-bound on the parallelism as required for scheduling of an application part within a given latency bound.…”

Section: Issue-width Estimationmentioning

confidence: 99%

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Exploring processor parallelism: Estimation methods and optimization strategies

Jordans

¹

,

Corvino

²

,

Jóźwiak

³

et al. 2013

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Abstract-Automatic optimization of application-specific instruction-set processor (ASIP) architectures mostly focuses on the internal memory hierarchy design, or the extension of reduced instruction-set architectures with complex custom operations. This paper focuses on very long instruction word (VLIW) architectures and, more specifically, on automating the selection of an application specific VLIW issue-width. The issuewidth selection strongly influences all the important processor properties (e.g. processing speed, silicon area, and power consumption). Therefore, an accurate and efficient issue-width estimation and optimization are some of the most important aspects of VLIW ASIP design. In this paper, we first compare different methods for the estimation of required the issue-width, and subsequently introduce a new force-based parallelism estimation method which is capable of estimating the required issue-width with only 3% error on average. Furthermore, we present and compare two techniques for estimating the required issue-width of software pipelined loop kernels and show that a simple utilization-based measure provides an error margin of less than 1% on average.

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ASAM: Automatic Architecture Synthesis and Application Mapping

Jóźwiak

¹

,

Lindwer

²

,

Corvino

³

et al. 2012

2012 15th Euromicro Conference on Digital System Design

Self Cite

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• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Index Terms-embedded systems, heterogeneous multiprocessor system-on-chip (MPSoC), customizable ASIPs, architecture synthesis, MPSoC and ASIP design automation;

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Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors

Cited by 3 publications

References 21 publications

ASAM: Automatic architecture synthesis and application mapping

ASAM: Automatic architecture synthesis and application mapping

Exploring processor parallelism: Estimation methods and optimization strategies

ASAM: Automatic Architecture Synthesis and Application Mapping

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