Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization

EMI Architectural Model and Core Hopping

“…Sehatbakhsh et al [19] were able to show a correlation between frequency spikes in EMI and the amount of time a loop takes to execute, which allows for zero-overhead spectral profiling. On similar lines, EM has been shown to correlate well with di dt voltage noise in post-silicon setups [11]. This correlation is used to predict voltage noise stress tests driven by EM amplitude and obtain resonance frequency of the power delivery LC-tank of a chip.…”

Exploiting intrinsic hardware guardbands and software heterogeneity to improve the energy efficiency of computing systems

“…Typically, such workloads consist of a periodic sequence of high activity and low activity instruction regions at a frequency equal to the resonance frequency of the power delivery network (50−200M Hz in modern CPUs). This pattern simulates the invocation of high CPU activity workloads immediately after a period of very low activity, which causes large di/dt swings and large voltage droops, as shown in prior work [103].…”

“…Moreover, on top of a realistic software stack, the background operating system activity (jitter) smooths out large voltage swings caused by such viruses [78]. To this end, we tried to produce large di/dt swings and large voltage droops by alternating phases of high and low activity at different frequencies, based on the findings of prior work [103]. We experimented on the Intel-based platforms, presented in the Chapter 2.…”

“…However, our effort did not result in tighter CPU voltage margins, compared to those identified by our characterization. This is attributed to the fact that all the Intel systems we experimented on, in contrast with the X-Gene 2 processor used in prior work [103], feature a Load Line Calibration (LLC) mechanism to mitigate such steep voltage swings.…”

Anatomy of microarchitecture-level reliability assessment for modern processors

“…Recently proposed techniques can not only detect errors but also identify symptoms of upcoming failures by monitoring both hardware and software metrics [128] [157] [158]. By considering all these aspects, and also the fact that many of these techniques are applicable to different platforms, we have developed HealthLog monitor, a generic framework that bridges the gap between different hardware mechanisms and software technologies and allows flexible combination of internal and external protection, detection and monitoring mechanisms for more efficient reactive and proactive error handling.…”