Leakage in CMOS Circuits – An Introduction

Helms, Domenik; Schmidt, Η. K.; Nebel, Wolfgang

doi:10.1007/978-3-540-30205-6_5

Cited by 22 publications

(12 citation statements)

References 18 publications

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“…From a system level view, the dominant leakage parameters [8] described in Section 1 can be identified and predicted. In [17], a flow for modeling the thermal dependence of the leakage was presented, and in [18,19], thermally dependent leakage estimation was combined with a chip-wide temperature prediction, thus also regarding the electro-thermal back-coupling introduced by the subthreshold current's thermal dependence.…”

Section: Related Workmentioning

confidence: 99%

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Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

Helms

Ehmen

Nebel

2006

Proceedings of the 2006 International Symposium on Low Power Electronics and Design - ISLPED '06

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In this work we present a SPICE-based RTL subthresholdleakage model analyzing components built in 70nm technology [1]. We present a separation approach regarding interand intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude [2,3]. We show that the leakage of RT-components still shows state dependencies between 20% and 80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed.

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Section: Related Workmentioning

confidence: 99%

“…To make leakage estimation accuracy comparable, our leakage models will have to regard all known parameters influencing leakage [8].…”

Section: Introductionmentioning

confidence: 99%

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

Helms

Ehmen

Nebel

2006

Proceedings of the 2006 International Symposium on Low Power Electronics and Design - ISLPED '06

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“…On the one hand, short-circuit power can be modeled in a similar way to dynamic power by introducing an equivalent capacitance [4]. On the other hand, leakage power is no longer negligible in current technologies and is being extensively studied by the scientific community [5]. However, only partial progress has been made in modeling and estimating internal power consumption by proposing approximate statistical analyses [6] or generalist behavioral models for the internal states of the gate [7], and no quantitative analysis has yet been found to demonstrate the relevance of this internal power consumption with respect to the total power consumption of a gate.…”

Section: Introductionmentioning

confidence: 99%

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

Millan

Juan

Bellido

et al. 2009

Lecture Notes in Computer Science

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Abstract. Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental set-up that shows that this power component may contribute up to 59% of the total power consumption of a gate in modern technologies. This fact makes very important to include it into any accurate power model. 1

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“…the frequency f within set F of applicable discrete frequency levels, and how many transistors are switching, i.e. on the code executed [57]. There are more influence factors such as temperature, but for simplification we assume that minimum possible voltage for a given frequency (and vice versa) are linearly related, and that for compute intensive tasks, the instruction mix is such that we know the average number of transistors switching.…”

Section: Energy Modelmentioning

confidence: 99%

Algorithms and Framework for Energy Efficient Parallel Stream Computing on Many-Core Architectures

Melot¹

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The rise of many-core processor architectures in the market answers to a constantly growing need of processing power to solve more and more challenging problems such as the ones in computing for big data. Fast computation is more and more limited by the very high power required and the management of the considerable heat produced. Many programming models compete to take profit of many-core architectures to improve both execution speed and energy consumption, each with their advantages and drawbacks. The work described in this thesis is based on the dataflow computing approach and investigates the benefits of a carefully pipelined execution of streaming applications, focusing in particular on off-and on-chip memory accesses. As case study, we implement classic and on-chip pipelined versions of mergesort for Intel SCC and Xeon. We see how the benefits of the on-chip pipelining technique are bounded by the underlying architecture, and we explore the problem of fine tuning streaming applications for many-core architectures to optimize for energy given a throughput budget. We propose a novel methodology to compute schedules optimized for energy efficiency given a fixed throughput target. We introduce Drake, derived from Schedeval, a tool that generates pipelined applications for Many-Core architectures and allows the performance testing in time or energy of their static schedule. We show that streaming applications based on Drake compete with specialized implementations and we use Schedeval to demonstrate performance differences between schedules that are otherwise considered as equivalent by a simple model. This work has been supported in parts by CUGS (the Graduate School in Computer Science, Sweden), Vetenskapsrådet, SeRC and EU FP7 EXCESS. Department of Computer and Information ScienceLinköping University SE-581 83 Linköping, Sweden Acknowledgements I would like to thank all members of PELAB for the inspiring and stimulating working environment as well as the passionate discussions around coffee or tea. In particular, my thanks to Kristian Sandahl for his efforts at maintening a strong group culture. Warm thanks to Christoph Kessler, for all fruitful discussions and ideas when my imagination came short, for his support and patience when results came late and for entrusting me with opportunities and responsibilities that taught me valuable experiences. Many thanks to Jörg Keller for sharing his ideas in details about my work, and for always carefully reviewing and challenging any hypothesis I proposed, as it repeatedly resulted in strengthening good ideas and discarding bad ones. I would like to thank all students who participated in the work, providing a precious help to progress. I am grateful to Intel for providing the Single Chip Cloud computer research prototype and their efforts to help in the numerous moments where nothing worked. Many thanks to the National Supercomputer Center (NSC) for providing powerful computing means to run my experiments, TUS for always providing a quick and precious technica...

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Leakage in CMOS Circuits – An Introduction

Cited by 22 publications

References 18 publications

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

Algorithms and Framework for Energy Efficient Parallel Stream Computing on Many-Core Architectures

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