Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's

Performance enhancement of offset gated polysilicon thin-film transistors

“…It is well known that the dominant leakage current mechanism is carrier emission via grain boundary traps by the high electric field near the drain [2]. In order to reduce the leakage current, conventional offset drain TFT structures are commonly used [3], [4]. However, usually the offset region adds to the structure a large parasitic series resistance which leads to a severe on-current reduction.…”

Asymmetric fingered polysilicon p-channel thin film transistor structure for kink effect suppression

“…It has been also proposed that hot carrier-induced defects could be generated at the grain boundaries, creating a damaged region close to the drain junction [5]. The usual approach to reduce both kink effect and HCE is to limit the impact ionization contribution decreasing the electric field at the drain junction, as in the case of drain offset [6], lightly doped drain (LDD) [7] and gate overlapped LDD (GOLDD) [3] structures. However, these architectures could influence the electrical device characteristics increasing parasitic resistance.…”

Formation of sub-micrometer polycrystalline-SiGe thin-film transistors by using a thinned channel layer

“…This is one of the bias-dependent issues caused by defects in poly-Si TFT devices, which cause poor switching characteristics such as low on/off current ratio [3][4][5][6][7]. It has been reported that various drain structures can decrease the leakage current in poly-Si TFTs due to reduction of electric field intensity near the drain region [8][9][10][11][12][13].…”