Self-heating effects are investigated in polycrystalline silicon thin film transistors by combining experimental measurements and two-dimensional numerical simulations. From the thermodynamic model the temperature distribution was extracted and found rather uniform along the channel. This allowed the authors to introduce a simplified method to determine the channel temperature when the device is affected by self-heating effects.
A systematic study has been made of the conduction process in polycrystalline-silicon thin film transistors (poly-Si TFTs) using carrier flow parallel and perpendicular to sub-grain-boundaries in sequentially laterally solidified material. The objective of this investigation was to obtain an unambiguous characterization of grain boundary (GB) behavior. By studying orthogonal TFTs in this anisotropic material, it was possible to distinguish grain boundary carrier trapping from intragrain trapping. In conventional poly-Si, the material is isotropic over distances greater than the grain size of ∼300nm, and there is no direct and clear-cut way of distinguishing between intragrain and intergrain trapping centers. In the experimental samples, the thermal activation energy of the channel current was measured in the two orthogonal directions, and the difference in activation energy was related to carrier flow over perpendicular sub-GBs. The detailed interpretation of the experimental results was facilitated by two-dimensional numerical simulations, demonstrating that a planar barrier GB, which simply resulted in a potential barrier within the channel, was fundamentally incompatible with the experimental drain current activation energy data. It was only possible to obtain a satisfactory representation of all the experimental data by using a finite width GB, in which carrier flow was controlled by transport across the resistive GB region, rather than by emission over a barrier. This representation of the sub-GB permitted the essential combination of reduced field effect mobility, for orthogonal carrier flow, and a drain current activation energy, which was close to zero.
An investigation has been undertaken of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using sequential laterally solidified material. This material has a location-controlled distribution of grain boundaries (GBs), which makes it particularly useful for the investigation of their influence on the performance of poly-Si TFTs, and to address the issue of the role of spatially localized trapping states. The experimental results showed that the specific location of the GBs had a minimal effect upon TFT performance, and most aspects of TFT performance could be accurately simulated using a spatially uniform distribution of states. The conclusion to arise from this study is that, with the exception of field-effect mobility, there are no features in the device behavior, which must be specifically attributed to the spatial localization of trapping states. A limited comparison with conventional laser-crystallized poly-Si was undertaken, and, in this material, it was found that the effects of trap localization were apparent.
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