Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P–V–T fluctuations

Wang, Jinhui; Gong, Na; Hou, Ligang; Peng, Xiaohong; Sridhar, R.; Wu, Wuchen

doi:10.1016/j.microrel.2011.06.011

Cited by 13 publications

(5 citation statements)

References 13 publications

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“…Six video samples were selected for this test, including Akiyo, Coastguard, Container, Foreman, Hall and Waterfall. These video samples are recommended by the Joint Collaborative Team on Video Coding (JCT-VC) [21,22]. I clipped the videos to 6 seconds long and invited 15 participants to watch these videos on a Samsung Galaxy Note 4 smartphone.…”

Section: Subjective Video Quality Testmentioning

confidence: 99%

Viewer-Aware Intelligent Mobile Video System for Prolonged Battery Life

Gao¹,

McCourt²,

Wang³

et al. 2018

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Section: Subjective Video Quality Testmentioning

confidence: 99%

Viewer-Aware Intelligent Mobile Video System for Prolonged Battery Life

Gao¹,

McCourt²,

Wang³

et al. 2018

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“…The leakage current in footless domino circuits is analyzed in standby mode, while keeping the clock high gated (Peiravi and Asyaei, 2013;Wang et al, 2011). Depending on the inputs of the domino circuit, there are two states, which are CHIH and CHIL.…”

Section: Related Workmentioning

confidence: 99%

Sleep signal controlled footless domino circuit for low leakage current

Pandey¹,

Gupta

Verma

2018

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Purpose This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents. Design/methodology/approach In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state. Findings The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits. Originality/value The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

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“…Steep SS devices are of great interest due to demand of power and energy‐efficient digital circuits. As metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) scaled below 45 nm, the subthreshold leakage current becomes more significant due to short‐channel effects (SCEs), parameter variations, and strong coupling between temperature and subthreshold leakage current . The fundamental thermodynamic limit on the minimum operational voltage and switching energy of the conventional FETs is ideally 60 mV/decade at room temperature, but in practice, the gate oxide screens the gate fields and the coupling between the gate and channel is not perfect, which causes SS to be larger than the ideal value .…”

Section: Introductionmentioning

confidence: 99%

A comprehensive analytical study of electrical properties of carbon nanotube field‐effect transistor for future nanotechnology

Singh

Murthy

Prabu

2017

Int J Numerical Modelling

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This paper discusses a comprehensive analytical study of electrical properties of single‐wall conventional carbon nanotube field‐effect transistor (CNTFET) devices of subthreshold swing (SS), transconductance (gm), and extension resistance. The analytical expressions for SS and gm have been derived based on channel modulated potential. In the study, it was observed that SS value of the CNTFET device is equal to 60 mV/decade, which is smaller than the conventional and double gate metal‐oxide‐semiconductor field‐effect transistors. The subthreshold swing degrades at larger tube's diameter and gate‐source voltage due to increased source‐drain leakage current. Carbon nanotube field‐effect transistor devices achieve larger gm at large gate‐source voltage, which has a disadvantage of reducing the allowable voltage swing at the drain. The extension resistance of the device falls with diameter of the tube.

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Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P–V–T fluctuations

Cited by 13 publications

References 13 publications

Viewer-Aware Intelligent Mobile Video System for Prolonged Battery Life

Viewer-Aware Intelligent Mobile Video System for Prolonged Battery Life

Sleep signal controlled footless domino circuit for low leakage current

A comprehensive analytical study of electrical properties of carbon nanotube field‐effect transistor for future nanotechnology

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