Leakage control through fine-grained placement and sizing of sleep transistors

Khandelwal, Vishal; Srivastava, Ashish

doi:10.1109/iccad.2004.1382635

Cited by 49 publications

(58 citation statements)

References 10 publications

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“…The most different thing is that FGSTI technique can be performed when the circuit speed is not influenced, while BBSTI technique will definitely induce certain circuit slowdown, about 5% or more for most combinational circuits [9]. Thus the FGSTI technique is changed into a slack distribution problem to determine which gate can be assigned with ST.…”

Section: Fig 1 Fine-grain Sleep Transistor Insertion Techniquementioning

confidence: 99%

“…Thus the FGSTI technique is changed into a slack distribution problem to determine which gate can be assigned with ST. Recently, [9] use a one-shot heuristic algorithm to determine where to put ST in a FGSTI design, but how to perform FGSTI technique isn't addressed when the circuit slowdown is 0% and the one-shot heuristic algorithm may easily fall into a local optimal result. Our previous work [7] presents a mixed integer programming (MLP) model for FGSTI technique.…”

Section: Fig 1 Fine-grain Sleep Transistor Insertion Techniquementioning

confidence: 99%

“…Suppose that I ON (v) is the current flowing through ST during the active mode, it can be expressed as given by [9]:…”

Section: Delay Modelmentioning

confidence: 99%

“…In addition, FGSTI technique leads to a smaller simultaneous switching current when the circuit changes between standby mode and active mode comparing to BBSTI technique. Furthermore, better circuit slack utilization can be achieved as the slowdown of each gate is not fixed, and then leads to a further reduction of leakage and area [7] [9].…”

Section: Introductionmentioning

confidence: 99%

“…MTCMOS technique can be mainly categorized into two approaches: block based sleep transistor insertion (BBSTI) technique [3][4][5][6] and fine-grain sleep transistor insertion (FGSTI) technique [7][8][9]. In BBSTI, all the gates in the circuits are clustered into sizable blocks and then these blocks are gated using large ST; all the gates are assumed to have a fixed slowdown.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization

Wang

Liu

Luo

et al. 2006

Lecture Notes in Computer Science

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Abstract. Fine-grain Sleep Transistor Insertion (FGSTI) is an effective leakage reduction method in VLSI design optimization. In this paper, a novel Genetic Algorithm (GA) based FGSTI technique is presented to decide where to put the sleep transistors (ST) when the circuit slowdown is not enough to assign sleep transistors everywhere in the combinational circuits. Penalty based fitness function with a built-in circuit delay calculator is used to meet the performance constraint. Although optimal FGSTI problem is proved to be NP-hard, our method can steadily give a flexible trade-off between runtime and accuracy. Furthermore a Successive Chromosome Initialization method is proposed to reduce the computation complexity when the circuit slowdown is 3% and 5%. Our experimental results show that the GA based FGSTI technique can achieve about 75%, 94% and 97% leakage current saving when the circuit slowdown is 0%, 3% and 5% respectively.

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Section: Fig 1 Fine-grain Sleep Transistor Insertion Techniquementioning

confidence: 99%

Section: Fig 1 Fine-grain Sleep Transistor Insertion Techniquementioning

confidence: 99%

“…Suppose that I ON (v) is the current flowing through ST during the active mode, it can be expressed as given by [9]:…”

Section: Delay Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization

Wang

Liu

Luo

et al. 2006

Lecture Notes in Computer Science

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Power Gating and Dynamic Voltage Scaling

Calhoun

Kao

Chandrakasan

Leakage in Nanometer CMOS Technologies

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Power-Gating for Leakage Control and Beyond

Calimera¹,

Macii²,

Macii³

et al. 2014

Circuit Design for Reliability

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The need of reliable nanometric integrated circuits is driving the EDA community to develop new automated design techniques in which power consumption and variability are central objectives of the optimization flow.Although several Design-for-Low-Power and Design-for-Variability options are already available in modern EDA suites, the contrasting nature of the two metrics makes their integration extremely challenging. Most of the approaches used to compensate and/or mitigate circuit variability (e.g., Dynamic Voltage Scaling and Adaptive Body Biasing) are, in fact, intrinsically power inefficient, as they exploit the concept of redundancy, which is known to originate power overhead.In this work, we introduce possible solutions for concurrent leakage minimization and variability compensation. More specifically, we propose Power-Gating as a mean for simultaneously controlling static power consumption and mitigating the effects induced by two of the most insidious sources of variability, namely, Process Variations (PV) due to uncertainties in the manufacturing and Transistor Aging due to Negative Bias Temperature Instability (NBTI).We show that power-gating, when implemented through the insertion of dedicated switches (called sleep transistors), has a double effect: On one hand, when sleep transistors are enhanced with tunable features, it acts as a natural supplyvoltage regulator, which implements a control knob for PV compensation; on the other hand, during the idle periods, it makes the circuits immune to NBTI-induced aging.We describe optimization techniques for the integration of a new concept of power-gating into modern sub-45 nm design flows, that is, Variation-Aware PowerGating. The experimental results we have obtained are extremely promising, since they show 100 % timing yield under the presence of PV and circuit lifetime extension of more than 5 in the presence of NBTI.

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Leakage control through fine-grained placement and sizing of sleep transistors

Cited by 49 publications

References 10 publications

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization

Power Gating and Dynamic Voltage Scaling

Power-Gating for Leakage Control and Beyond

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