Latchup prevention using an N-well epi-CMOS process

Holly, P.; Akers, L.A.

doi:10.1109/t-ed.1983.21308

IEEE Trans. Electron Devices

1983

DOI: 10.1109/t-ed.1983.21308

|View full text |Cite

Latchup prevention using an N-well epi-CMOS process

P. Holly

L.A. Akers²

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

1986

2009

Publication Types

Select...

Article5

Relationship

Self Cite0

Independent5

Authors

Journals

Cited by 5 publications

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Latch‐up in CMOS circuits: A review

Sangiorgi¹

1990

Trans Emerging Tel Tech

View full text Add to dashboard Cite

In CMOS technologies, rapidly becoming the most important ones for VLSI microelectronics, the inherent phenomenon of latch‐up, represents one of the most serious limitations for further dimension scaling in the deep sub‐micron range. For this reason latch‐up has attracted a lot of attention in the last decade and a deep understanding of its essential features has been achieved, although a few specific problems are still to be satisfactorily solved.

show abstract

Latch‐up in CMOS circuits: A review

Sangiorgi¹

1990

Trans Emerging Tel Tech

View full text Add to dashboard Cite

show abstract

Improvement of latchup hardness by geometry and technology tuning

Mazuré

Reczek

Takacs

et al. 1988

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Integrated Silicon PIN Photodiodes Using Deep N-Well in a Standard 0.18-$\mu$m CMOS Technology

Çiftçioğlu

Zhang

et al. 2009

J. Lightwave Technol.

View full text Add to dashboard Cite

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

hi@scite.ai

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

Latchup prevention using an N-well epi-CMOS process

Cited by 5 publications

References 10 publications

Latch‐up in CMOS circuits: A review

Latch‐up in CMOS circuits: A review

Improvement of latchup hardness by geometry and technology tuning

Integrated Silicon PIN Photodiodes Using Deep N-Well in a Standard 0.18-$\mu$m CMOS Technology

Contact Info

Product

Resources

About