Latch-Based Performance Optimization for Field-Programmable Gate Arrays

Teng, Bill; Anderson, Jason

doi:10.1109/tcad.2012.2235913

Cited by 5 publications

(1 citation statement)

References 33 publications

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“…Although the overhead of a latch is very small, they are not commonly used in digital designs, because of some limitations such as difficult timing analysis and high susceptibility to hold time violations (HTVs). In [7], the HTV problem of latches is mitigated by reducing the clock duty cycle. However, the use of a nonstandard clock signal in these pulsed latches could have other difficulties.…”

Section: Related Workmentioning

confidence: 99%

Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations

Nejat

Alizadeh

Afzali-Kusha

2015

IEEE Trans. VLSI Syst.

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Dynamic flip-flop (FF) conversion is a method of time borrowing (TB) for improving the performance of digital systems prone to variations. The first type of this method (Type A), which was previously presented, suffers from a large inefficient transparency window. In this brief, we present an improved structure for this method (Type B) that mitigates this problem by automatically closing the window after the arrival of late data at timing critical FFs. This method was compared with soft edge FF and dynamic clock stretching through simulations on different ITC'99 benchmarks. We defined a parameter called improvement efficiency, which is the ratio of the timing yield improvement to the power overhead of TB. According to the simulation results, the efficiency of Type A is on average 269% more than the best results of other methods when considering only the setup time violations. But, when taking both the setup time and the hold time violations into account, Type B is on average 46% more efficient than the best results of other methods. The simulations also show that the yield improvement of this method increases in higher clock frequencies and it remains the most efficient method when reducing the voltage down to near-threshold region.

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Section: Related Workmentioning

confidence: 99%

Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations

Nejat

Alizadeh

Afzali-Kusha

2015

IEEE Trans. VLSI Syst.

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A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architecture

Arumugam¹,

Viswanaathan²

2016

Circuit Theory & Apps

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SummaryClock distribution networks consume a significant amount of the whole chip power budget. Therefore, reduction in the power consumption of the clock networks is a significant objective in high‐performance Integrated Circuit (IC) designs. This paper presents a novel Particle Distance Weighted Clustering (PDWC)‐Unity Clustering Optimization (UCO) algorithm for the placement of clock buffers in the Field Programmable Gate Array (FPGA) architecture. A novel PDWC algorithm is applied for clustering the logical components based on the minimum distance between components. A UCO algorithm is developed to determine the location for the placement of the buffers. This clustering technique reduces the delay rate of the architecture because of the minimum number of logical components. The overall area and power consumption of the FPGA architecture are reduced because of the placement of the buffers and latches. Our proposed PDWC‐UCO algorithm achieves lower delay, power consumption, wire length, latency and skew than the existing Flip‐Flop (FF) merging and register clustering algorithms. Copyright © 2016 John Wiley & Sons, Ltd.

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Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming

Zgheib

Ganusov

2021

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)

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Latch-Based Performance Optimization for Field-Programmable Gate Arrays

Cited by 5 publications

References 33 publications

Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations

Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations

A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architecture

Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming

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