A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architecture

Abstract

SummaryClock distribution networks consume a significant amount of the whole chip power budget. Therefore, reduction in the power consumption of the clock networks is a significant objective in high‐performance Integrated Circuit (IC) designs. This paper presents a novel Particle Distance Weighted Clustering (PDWC)‐Unity Clustering Optimization (UCO) algorithm for the placement of clock buffers in the Field Programmable Gate Array (FPGA) architecture. A novel PDWC algorithm is applied for clustering the logical components based on the minimum distance between components. A UCO algorithm is developed to determine the location for the placement of the buffers. This clustering technique reduces the delay rate of the architecture because of the minimum number of logical components. The overall area and power consumption of the FPGA architecture are reduced because of the placement of the buffers and latches. Our proposed PDWC‐UCO algorithm achieves lower delay, power consumption, wire length, latency and skew than the existing Flip‐Flop (FF) merging and register clustering algorithms. Copyright © 2016 John Wiley & Sons, Ltd.