K-band CMOS power amplifier with adaptive bias for enhancement in back-off efficiency

Abstract

A K-band power amplifier that dynamically adjusts the dc consumption based on the output power is presented. Compared with a fixed-bias PA that consumes a constant dc power of 265 mW, the proposed PA saves 157 mW at quiescent state and 88 mW when operated at P 1dB 6-dB back-off, and the OP 1dB of the PA is also extended. This is the first CMOS PA with effective enhancement in back-off efficiency near MMW region.

High-Gain and Low-Power Power Amplifier for 24-GHz Automotive Radars

“…As shown in Table 1, the OIP3 is good linearity of 16.5 dBm. The proposed circuit showed highest power gain of 24.04 dB, the highest saturated power gain of 21.5 dBm, the lowest input/output return loss of -18.2 dB/-20.1 dB, the lowest power dissipation of 44.3 mW, and the smallest chip size of 0.12 mm 2 as compared to recently reported research results in [11][12][13][14].…”

“…In the last 15 years, silicon-based 24-GHz short-range automotive radars have been investigated both by industry and academia [1][2][3][4][5][6]. Therefore, next generation radar sensors may well be required to support 24-GHz band for compatibility and lower overall cost [7][8][9][10][11][12][13][14].…”

Study of CMOS power amplifier design techniques for ka-band applications

“…This PA has a P1dB of 16.8 dBm with 15.5% PAE at 21 GHz, and the peak PAE is 18.9% while the output power is 18 dBm. In 2011, [10] proposed power amplifier with adaptive bias for enhancement in back off efficiency as shown in Figure 5. In this design, two diode-connected transistors are inversely shunted at the gate of the CS stages and with quiescent bias voltage of 0.…”

“…Figure 5. CMOS power amplifier with adaptive bias [10] In 2012, [11] proposed two stages cascode device with input, output, and inter-stage matching networks as shown in Figure 6. In order to achieve maximum output power, the transistors (M3, M4) of the second stage are 64 fingers with unit finger width of 6 11m.…”

A 12 to 24 GHz high efficiency fully integrated 0.18 µm CMOS power amplifier

“…Improving the power added efficiency (PAE), the output power and the group delay are challenging tasks in the CMOS power amplifier design [3]. Different techniques such as using adaptive biasing techniques [4], and reversed body bias technique [5] were reported to increase the PAE for narrow band 24 GHz power amplifiers. Alternatively, in this work, the PAE is maximized over a wideband by optimizing the matching circuits around the band of interest.…”