K-Algorithm: An Improved Booth's Recoding for Optimal Fault-Tolerant Reversible Multiplier

Novel low-cost and fault-tolerant reversible logic adders

“…So far, many reversible arithmetic operators have been designed to perform addition [5][6][7][8][9][10][11][12] and multiplication [3,[13][14][15][16][17] that some of them are parity preserving and thus beneficial for fault-tolerant reversible circuits. In addition, some designs include proposing new gates and then utilizing them in the proposed adder or multiplier circuit such as [9,10,12,13] , and the others are based on exploiting the new arrangements of the existing gates.…”