Reversible logic based multiplication computing unit using binary tree data structure

Kotiyal, Saurabh; Thapliyal, Himanshu; Ranganathan, N.

doi:10.1007/s11227-015-1410-3

Cited by 22 publications

(8 citation statements)

References 24 publications

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“…It is necessary for any designer to choose designs based on their performance over a wide range of operand width. We found that the recent publication on multiplier in [38] discussed N xN reversible multiplier design. We considered the designs proposed in [38,39] and compared it with our work, as the efforts in both of these papers were to reduce the number of constant inputs and garbage outputs.…”

Section: Fredkin Gate (Frg)mentioning

confidence: 91%

“…Hence, we compared our design with other N xN reversible designs that are available in the literature. The designs proposed in [38] and [39] show the calculation for N xN reversible multiplier. In both of these papers, the authors have shown only the ancilla inputs and garbage outputs calculations; the comparisons shown in Tables I, II list only ancilla inputs and garbage outputs for these papers.…”

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

“…Our proposed design showed a better improvement in terms of the ancilla inputs resulting in saving the chip area since the number of lines are reduced. We have listed the garbage outputs of the designs proposed in [38] and [39]. Our design outperforms the existing designs because it is 100% better in terms of garbage outputs since our design produces no garbage.…”

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

“…We compared our design with another garbageless reversible multiplier design using the recursive scheme in [40]. Here, we compare our work with [38], [3]-R.Zhou et.al [39] Karatsuba multiplier design presented in [40]. The comparison for gate count, ancilla inputs, and delay are shown in Table III.…”

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

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Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

et al. 2016

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Abstract-A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are essential in designing an efficient quantum circuit. In the literature, there are multiple designs that have been proposed for a reversible multiplication operation. A multiplication hardware is essential for the circuit design of quantum algorithms, quantum cryptanalysis, and digital signal processing (DSP) applications. The existing designs of reversible quantum integer multipliers suffer from redundant garbage qubits. In this work, we propose a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier. The proposed quantum integer multiplier utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm. The proposed design methodology is the modified version of a conventional shift and add method. The proposed design of the quantum integer multiplier incorporates add or no operation based on multiplier qubits and followed by a rotate right operation. The proposed design of the quantum integer multiplier produces zero garbage qubits and shows an improvement ranging from 60% to 90% in ancilla qubits count over the existing work on reversible quantum integer multipliers.

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Section: Fredkin Gate (Frg)mentioning

confidence: 91%

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

See 2 more Smart Citations

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

et al. 2016

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“…In the last decades, some of the arithmetic operations such as multiplication [10,11], counter [12,13], and division [14] are designed as reversible circuits that would be applied in some nanotechnology systems. The optimized and fault-tolerant design of reversible barrel shifters is presented by Shamsujjoha et al [40], which applies low power MOS transistors.…”

Section: Introductionmentioning

confidence: 99%

Novel reversible CLA, optimized RCA and parallel adder/subtractor circuits

Gharajeh

Haghparast

2020

Serb J Electr Eng

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This paper proposes reversible circuit designs of the three most commonly used adders: carry look-ahead adder (CLA adder), ripple carry adder (RCA adder), and parallel adder/subtractor. The n-bit reversible CLA adder, called CLA-GH, is designed using the Peres and Fredkin gates. The n-bit optimized reversible RCA adder, called ORCA-GH, is designed using the reversible circuit of a parity-preserving reversible full adder. Both circuits reduce the quantum cost. However, the ORCA-GH circuit also improves the number of constant inputs. Furthermore, the n-bit reversible parallel adder/subtractor, called PAS-GH, is designed using the Feynman, Peres, and Fredkin gates. It decreases the number of garbage outputs and quantum cost. The transistor realizations of the CLA-GH and PAS-GH circuits are provided accordingly. The evaluation results indicate that the proposed circuits surpass the existing works in all figures of merit.

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Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates

Thapliyal

2016

Lecture Notes in Computer Science

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Reversible logic based multiplication computing unit using binary tree data structure

Cited by 22 publications

References 24 publications

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

Novel reversible CLA, optimized RCA and parallel adder/subtractor circuits

Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates

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