Junctionless Gate-All-Around pFETs Using &lt;italic&gt;In-situ&lt;/italic&gt; Boron-Doped Ge Channel on Si

Wong, I-Hsieh; Chen, Yen‐Ting; Huang, Sung-Wei; Tu, Wen‐Hua; Chen, Yu‐Sheng; C, Liu

doi:10.1109/tnano.2015.2456182

Cited by 26 publications

(8 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A key feature is that the conduction band has s-orbital like symmetry and the valence band has p-orbital like symmetry. We focus on the valence band structure of Ge owing to its versatile applications on high-mobility transistors [92], SOC [93], and qubit devices [15,16,29].…”

Section: Hole Effective Mass In Ge 2dhgmentioning

confidence: 99%

Recent progress in undoped group-IV heterostructures for quantum technologies

Tai,

2024

Mater. Quantum. Technol.

View full text Add to dashboard Cite

Silicon has been a core material for digital computing owing to its high mobility, stability oxide interface, mature manufacturing technologies for more than half a century. While Moore’s law seems to further advance via various technologies to extend its expiration date, some intractable problems that requires processing times growing exponentially cannot be solved in a reasonable scale of time. Meanwhile, quantum computing is a promising tool to perform calculations much more efficiently than classical computing for certain types of problems. To realize a practical quantum computer, quantum dots on group-IV semiconductor heterostructures are promising due to the long decoherence time, scalability, and compatibility with the Si VLSI technology. In this review, we start with the advancement of group-IV undoped heterostructures since 2000 and review carrier transport properties in these undoped heterostructure. We also review the hole effective masses, spin-orbit coupling, and effective g-factors in the Ge-based heterostructures and conclude with a brief summary.

show abstract

Section: Hole Effective Mass In Ge 2dhgmentioning

confidence: 99%

Recent progress in undoped group-IV heterostructures for quantum technologies

Tai,

2024

Mater. Quantum. Technol.

View full text Add to dashboard Cite

show abstract

“…16 Due to bulk conduction mechanism of JLFET, the ON-state current (I ON ) of JLFET is large and have tremendous driving capabilities. High doping can increase the ON-state current, but it also boosts OFF-state current, [17][18][19][20][21][22][23] hence ON-state to OFF-state current ratio of JLFET is reduced. To make the channel fully depleted, a gate electrode with large workfunction is used.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis of short channel effects immune JLFET with enhanced drive current

Raj¹,

Singh

Sharma³

2023

Int J Numerical Modelling

View full text Add to dashboard Cite

This manuscript reports analog/RF and noise analysis of a novel junctionless field effect transistor. To reduce the gate induced drain leakage (GIDL), step‐gate‐oxide structure is used with a high‐k buried oxide (BOX) which subsequently reduces IOFF. The off current and gate capacitance is reduced by including step‐gate‐oxide in high k‐BOX JLFET due to increase in the band to band tunneling (BTBT) width. The DIBL is reduced significantly to 0.014 which is 60% less as compared to high‐k BOX JLFET (HB JLFET). For different length and thickness of the step‐gate‐oxide, the analog/RF and noise performance of the step‐gate‐oxide JLFET with high‐k BOX (SGO HB JLFET) have also been investigated in detail. Silvaco TCAD simulation of the proposed structure for 20 nm channel length shows an extremely high ION/IOFF ratio of ~108. The subthreshold swing for the simulated structure was also found to be considerably low (82 mV/dec).

show abstract

“…However, at the nano range, devices show challenges in terms of complexity in fabrication due to doping concentration gradient. On the other hand, devices such as Junctionless Field Effect Transistors (JLFETs) [1][2][3][4][5][6][7][8][9][10][11][12][13][14] have constant doping in the source length, channel, and drain length region, reducing fabrication complexity. A junctionless transistor was first reported in 2009 by J.P. Collinge [15].…”

Section: Introductionmentioning

confidence: 99%

An Analytical Model for the Depletion Region Width and Threshold Voltage of a Parallel Gated Junctionless Field Effect Transistor

Raibaruah¹,

Sarma²

2022

J. Nano- Electron. Phys.

View full text Add to dashboard Cite

This paper reports on the modeling of the depletion region width and threshold voltage of a parallel gated junctionless field effect transistor. The depletion region width is obtained by resolving 1D Poisson equation along the channel of the device in the y-direction. The central potential through the channel region of the device is also considered. With the help of the depletion region width and device central potential model, the threshold voltage of the device is obtained. Exploration has been made for different variations of the depletion width depending on the gate to source voltage, gate oxide thickness, and different gate dielectric materials. For a 0.6 V gate bias, a 4 nm depletion width is achieved. The threshold voltage variation is obtained and analyzed by considering different drain voltages, doping concentrations, temperatures, and work functions. The device at 10 19 cm -3 doping concentration, 300 K temperature, and 5.4 eV work function with a drain voltage of 1 V allows a threshold voltage of 0.47 V.

show abstract

Junctionless Gate-All-Around pFETs Using <italic>In-situ</italic> Boron-Doped Ge Channel on Si

Cited by 26 publications

References 17 publications

Recent progress in undoped group-IV heterostructures for quantum technologies

Recent progress in undoped group-IV heterostructures for quantum technologies

Performance analysis of short channel effects immune JLFET with enhanced drive current

An Analytical Model for the Depletion Region Width and Threshold Voltage of a Parallel Gated Junctionless Field Effect Transistor

Contact Info

Product

Resources

About