Jitter tolerance calibration for high-speed serial interfaces

Multi-data rate receiver for high-speed serial interfaces

“…PJ which is also referred to as sinusoidal jitter (SJ), is mainly caused due to interferences to the data signal related to ground bounce or power supply noise [48], [53], [68]. Finally, BUJ is generated by crosstalk due to coupling from neighboring channels or digital switching noise, which is uncorrelated with data [48], [154].…”

“…BER measurements require large data sample but since RJ is a Gaussian process, its peak-to-peak value increases with sample size. For a given BER budget and in the absence of DJ the crest factor QBER correlates peak-to-peak random jitter RJpp with RJrms where, 2QBER=RJpp/RJrms [14], [69], [154].…”

“…High speed link transceivers jitter performance verification, requires system modelling in high level description languages like Verilog-AMS, verilog-A [59] or similar in order to: a) be able to implement and easily parameterize the jitter noise sources, b) speed up the verification simulations, c) co-simulate both transistor level building blocks and behavioural modules, d) generate the desired metrics, like jitter tolerance mask or BER [60] and e) accelerate the circuit design process. There are several published works which implement the jitter behavioral modelling of HSSI's building blocks employing verilog-AMS, such as the digital clock and data recovery circuit presented in [61] and high speed phase-locked loop presented in [62], [154].…”

“…Also a pattern generator model for jitter tolerance simulation and a high-speed wired link system verification method are presented in [65] and [66], respectively. The disadvantages of the aforementioned works are: a) the jitter noise components are not related with any HSSI standard specifications, b) the jitter ingredients of different frequency bands are not taken into account and c) the jitter sources are not calibrated in order to be compliant with any HSSI standard [154].…”

“…Also, the proposed Jitter generator can be employed as a platform to easily explore different receiver architectures at the early design stages, rapidly perform system-level verification and co-simulate IC parts, which strongly depend on technology scaling (e.g. input buffer) [154].…”