Jitter analysis of high-speed sampling systems

Abstract

This paper describes the jitter analysis of such practical sampling systems as A-to-D converters, sample-and-hold circuits, and samplers. A new model for estimating jitter is proposed. In this model, total jitter is composed of sampling circuit jitter, analog input signal jitter, and sampling clock jitter. Using this model, jitter is broken up into three components. To evaluate the model, a precise method for measuring jitter is devised. This method is based on sampling sine-wave signal-to-noise ratio calculations, and it enables separation of jitter and amplitude noise. Finally, the performance limit of converters is discussed as evaluated by the model.

Sinusoidal Clock Sampling for Multigigahertz ADCs

“…Because N is already close enough to calculate the third order harmonic, the Taylor series expansion on the right side of (7) gives (8) The third-order harmonic is usually the dominant distortion component for a differential input, so for a T/H circuit with input-dependent sampling error, the SFDR can be estimated as SFDR (9) Observe that the SFDR is proportional to the square of the clock amplitude , inversely proportional to the square of the clock transition time , input signal swing A, and input signal frequency .…”

“…For an ADC with a sampling rate above GS/s, a high-speed track-and-hold (T/H) circuit is typically used in the front-end, followed by time-interleaving sub-ADCs [2]- [9]. In order to meet the stringent performance requirements of such ADCs (multi-gigahertz sampling rate, 5-8 bits resolution), the T/H circuit requires high linearity and wide bandwidth.…”

“…In order to meet the stringent performance requirements of such ADCs (multi-gigahertz sampling rate, 5-8 bits resolution), the T/H circuit requires high linearity and wide bandwidth. Furthermore, the performance of the ADC is usually limited by the jitter of the sampling clock [7]- [9]. Even a small sampling uncertainty can introduce a large error in the sampled voltage, resulting in harmonic distortion at the output.…”

Research of 100 MHz ultra-low-jitter clock generating circuit

“…2,3 However, few paper discuss about how to suppress the random jitter of signal generating circuit. In our paper, the 100 MHz signal generating circuit with ultra-low jitter and phase noise is studied, and the expression for jitter based on the loaded quality factor (Q L ) of circuit components is conducted by using the classical Leeson model, in combination with the relationship between the phase noise and the jitter.…”

“…Signal jitter will reduce the signal-to-noise ratio of the electronic system, deteriorate the resolution of the sampling system, and low down dynamic range. [1][2][3][4] In a communication system, jitter will also reduce the channel width and affect the bit error rate of data transmission. 5 From a viewpoint of construction, jitter is produced by the superposition of random jitter and deterministic jitter.…”