Jitter Amplification Characterization of Passive Clock Channels at 6.4 and 9.6 Gb/s

Chaudhuri, S.; Anderson, Warren; Bryan, James D.; McCall, James A.; Dabral, S.

doi:10.1109/epep.2006.321168

Cited by 23 publications

(16 citation statements)

References 3 publications

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“…One way to quantify this jitter coupling between edges, and the resulting jitter amplification, is through the so-called jitter impulse response [1] while the more intuitive approach is to simply recognize that jitter on an edge translates to voltage noise at neighboring edges in proportion to the slope of the channel step response at the appropriate time offset. For example, if the step response still has a slope of +lmV/ps at one clock period delay after its 50% point then +Ips ofjitter on a rising edge will cause, through voltage superposition, a "residual" voltage noise of -lmV on the next rising edge of the clock.…”

Section: Il Simulation Of Jitter Amplification For Sj and Rjmentioning

confidence: 99%

“…As a result, the Tx jitter will be amplified by the channel. Jitter Amplification, defined as the ratio of the output to the input jitter, can be very large, as described in [1], where jitter amplification is quantified through the so-called jitter impulse response. In this paper, we first offer an alternative way of explaining the physics of jitter amplification.…”

Section: Introductionmentioning

confidence: 99%

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Jitter Amplification Considerations for PCB Clock Channel Design

Madden

Chang

et al. 2007

2007 IEEE Electrical Performance of Electronic Packaging

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Jitter Amplification is a real concern in the design of PCB clock channels if the frequency of the clock is high and the PCB trace is relatively long. In this paper, we confirm the earlier finding of clock channel jitter amplification [1], using a multiple edge response (MER) simulation method instead of jitter impulse response for the channel. However, we show that both white Random Jitter (wRJ) and Sinusoidal Jitter (SJ) amplification are a function of the signal loss in the channel, and as such, are reduced significantly with equalization. Furthermore, simulated CMOS Tx RJ, which is dominated by its low frequency components, is amplified less than is wRJ, even for channels with >20dB signal loss. Measurement results are correlated with simulations for 2-6 GHz clocks on a channel containing 24-inches of PCB trace.

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Section: Il Simulation Of Jitter Amplification For Sj and Rjmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Jitter Amplification Considerations for PCB Clock Channel Design

Madden

Chang

et al. 2007

2007 IEEE Electrical Performance of Electronic Packaging

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“…High-frequency channel loss ( Figure 5) also impacts the jitter performance of source synchronous links, as the low-pass channel response causes input jitter to be amplified in a high-pass manner [8,9]. In order to investigate channel clock jitter amplification, consider the following time domain expression for a clock signal at frequency f c that contains a sinusoidal jitter component with amplitude J p and frequency f j :…”

Section: Channel Clock Jittermentioning

confidence: 99%

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

Liu

Chiang

et al. 2011

Journal of Electrical and Computer Engineering

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High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking architecture of high-speed source synchronous links. Tradeoffs in complexity and jitter tracking performance of common per-channel de-skew circuits are discussed, along with how band-pass filtering can be leveraged to provide additional jitter filtering at the receiver. Jitter tolerance analysis for a 10 Gb/s system shows that a near all-pass delay-locked loop (DLL) and phase-interpolator-(PI-) based de-skew performs best under low skew conditions, while, at high skew, architectures which leverage band-pass clock filtering or a phase-locked loop (PLL) for increased jitter filtering are more suitable. De-skew based on injection-locked oscillators (ILOs) offer a reduced complexity design and competitive jitter tolerance over a wide skew range.

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“…High frequency jitter can be severely amplified by lossy channels [5]. Hence, both duty cycle error on the Controller and quadrature phase error on the DRAM must be minimized.…”

Section: Duty-cycle and Quadrature Correctionmentioning

confidence: 99%

“…To further alleviate the speed limitation of the silicon, half rate and quadrature clocking are employed on the Controller and DRAM, respectively, to reduce the on-chip clock rates. Since high frequency jitter is amplified when passing through a low pass channel [5], duty cycle correction and quadrature correction are employed in the Controller and DRAM respectively to reduce deterministic jitter (DJ). The speed limitation of the silicon exacerbates another type of jitter, namely power-supply induced jitter (PSIJ) which cannot be alleviated with multi-phase clocking.…”

mentioning

confidence: 99%

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

Lee

Chang

Chun

et al. 2009

IEEE J. Solid-State Circuits

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Abstract-This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following technology ingredients: asymmetric equalization, asymmetric timing calibration, asymmetric link margining, inductor based (LC) PLLs, multi-phase error correction, and a data dependent regulator. At 16 Gb/s, this interface achieves a unit-interval to inverter FO4 ratio of 2.8 (Controller) and 1.4 (DRAM) and operates in a channel with 15 dB loss at Nyquist. Under such bandwidth limitations on and off chip, the Controller and DRAM PHYs consume 13 mW/Gb/s and 8 mW/Gb/s, respectively. Using PRBS 2 11 1, the link achieves a timing margin of 0.19 UI at a BER of 1e-12 for both read and write operations.

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Jitter Amplification Characterization of Passive Clock Channels at 6.4 and 9.6 Gb/s

Abstract: SUBMISSION ABSTRACT:Jifter amplification characteristics of different forwarded clock channels at 6.4 and 9.6 Gb/s are illustrated with model correlations.The effect illustrates the need for quarter rate clocking at higher speed, in lossy serial links.

Cited by 23 publications

References 3 publications

Jitter Amplification Considerations for PCB Clock Channel Design

Jitter Amplification Considerations for PCB Clock Channel Design

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

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