JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard

Kovač, Mario; Ranganathan, N.

doi:10.1109/5.364464

Cited by 99 publications

(42 citation statements)

References 27 publications

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“…Agostini et al [7] propose a 2D-DCT architecture based on the previous work of Kovac et al [8]. The authors decompose the transform in two 1D-DCT calculations with a transpose buffer thanks to the separability property.…”

Section: Related Workmentioning

confidence: 99%

A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs

Tumeo

Monchiero

Palermo

et al. 2007

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

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Multimedia applications, and in particular the encoding and decoding of standard image and video formats, are usually a typical target for Systemson-Chip (SoC). The bi-dimensional Discrete Cosine Transformation (2D-DCT) is a commonly used frequency transformation in graphic compression algorithms. Many hardware implementations, adopting disparate algorithms, have been proposed for Field Programmable Gate Arrays (FPGA). These designs focus either on performance or area, and often do not succeed in balancing the two aspects.In this paper, we present a design of a fast 2D-DCT hardware accelerator for a FPGA-based SoC. This accelerator makes use of a single seven stages 1D-DCT pipeline able to alternate computation for the even and odd coefficients in every cycle. In addition, it uses special memories to perform the transpose operations. Our hardware takes 80 clock cycles at 107MHz to generate a complete 8x8 2D DCT, from the writing of the first input sample to the reading of the last result (including the overhead of the interface logic). We show that this architecture provides optimal performance/area ratio with respect to several alternative designs.

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Section: Related Workmentioning

confidence: 99%

A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs

Tumeo

Monchiero

Palermo

et al. 2007

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

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“…The values (½ u l ) and (½ v l ) are calculated just as shown in ( 6), wherefore the same RAC-units as in Figure 2 can be utilized. Instead of a preprocessing unit in the case of the 1D-DCT, here a postprocessing device is needed, which calculates the results x l out of the u l and v l .…”

Section: The Architecture 31 Forward and Inverse Dctmentioning

confidence: 99%

“…The compression results were compared with the output from a software reference encoder 6 , whose compression options were disabled. Except for a slightly different generation scheme of interframes, the functionality of the software encoder was comparable to our application 7 .…”

Section: Performancementioning

confidence: 99%

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An FPGA-based video compressor for H.263 compatible bit streams

Lienhart

Männer

Noffz

et al. 2001

Proceedings of the 2001 ACM/SIGDA Ninth International Symposium on Field Programmable Gate Arrays

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This paper presents an FPGA architecture for video encoding according to the H.263 standard for video teleconferencing systems. The implementation is based on an off-the-shelf FPGA 1 and is embedded in a PCI plug-in card 2 with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, was implemented. The strategies, which have been applied to build the complex encoding operations, are treated in this paper. The complete application is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time operation of several video streams in a single reconfigurable chip. Enhanced coding options can also become implemented with present-day FPGAs. The use of FPGA technology enables the adaptation of hardware to various protocols and environments by software and therefore saves development time and hardware costs.

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“…27.3.2) is implemented as a sequence of two 1D-DCTs with a transpose matrix in between. The 1D-DCT is based on the algorithm proposed in [2] and consists of five 15b adder/subtractors and one 15b multiplier. The 2D-DCT output needs to be scaled by a scaling matrix afterwards, but this is performed without extra hardware, as it is incorporated in the quantization by scaling the quantization coefficients in advance.…”

mentioning

confidence: 99%

27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS

Reynders

Dehaene

2014

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

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Operating circuits in the near-threshold region enables large energy savings. However, such circuits also pose many challenges, such as increased delay, unwanted leakage paths and high sensitivity to variations. Working in advanced nanometer CMOS technologies compromises the robustness of circuits even more due to the increased variability. Nonetheless, these technologies offer higher operating frequencies for ultra-low-voltage circuits. Transitioning to smaller technologies is attractive for digital near-threshold circuits, provided that the impact of the increased variability can be mitigated. Few prior works have considered the design of variation-resilient ultra-low-voltage circuits in CMOS technologies smaller than 65nm. The aim of this work is to design a large system that advances the state-of-the-art by not only reaching very low energy consumption, but also clock frequencies of tens of MHz, while providing high variation resilience. We present a full JPEG encoder fabricated in a 40nm CMOS technology, fully functional down to a supply voltage of 210mV. The JPEG encoder is able to operate at clock frequencies in a range from 5 to 275MHz for supplies from 210 to 550mV, and thus achieves very high ultra-low-voltage speed. At the minimum-energy point (MEP), the JPEG encoder consumes only 29.01pJ/pixel at an operating frequency of 41MHz (V DD =330mV). The variation (σ/μ) of 26 dies at this point is only 9.4% for the frequency and 6.0% for the energy consumption.

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JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard

Cited by 99 publications

References 27 publications

A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs

A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs

An FPGA-based video compressor for H.263 compatible bit streams

27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS

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