Issue logic for a 600-MHz out-of-order execution microprocessor

Farrell, Jamie; Fischer, T.C.

doi:10.1109/4.668985

Cited by 69 publications

(39 citation statements)

References 2 publications

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“…We use a wired-OR style wakeup logic array ( [2], [8]). Dependencies are indicated using an instructionsinstruction (each wakeup-matrix row and each wakeup-matrix column corresponds to an instruction inserted into the issue queue) wakeup matrix [2] (or physical registers-instructions wakeup matrix [8]).…”

Section: Wakeup Logicmentioning

confidence: 99%

An Enhancement for a Scheduling Logic Pipelined over two Cycles

Tejero

Morancho

Olivé

et al. 2006

2006 International Conference on Computer Design

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-Out of order processors use the dynamic scheduling logic both to expose and to exploit parallelism. Pipelining this logic may sacrifice the ability to execute dependent instructions in consecutive cycles. Several previous studies have shown that pipelining the scheduling logic over two cycles degrades performance; our evaluations, in a 4-way machine, on SPEC-2000 integer benchmarks show a performance degradation about 11% compared to an unpipelined scheduling logic.In this work, we present two non-speculative enhancements for a scheduling logic pipelined over two cycles. The idea is computing in advance which instructions will be woken-up by all instructions that are currently competing for selection. Once all of them have been selected, the pre-computed group of instructions can compete for selection in next cycle. The enhancement goal is to tolerate the scheduling-loop latency when not enough ILP is available through the scheduling of dependent instructions in consecutive cycles.Our results in a 4-way machine show that our two proposed enhancements perform, on average, slightly better than two previously proposed speculative schedulers. The performance of our proposals is within a 2.6% and 2% of an unpipelined ideal scheduler.Index Terms -Back-to-back execution, dynamic scheduler, pipelined scheduling logic.

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Section: Wakeup Logicmentioning

confidence: 99%

An Enhancement for a Scheduling Logic Pipelined over two Cycles

Tejero

Morancho

Olivé

et al. 2006

2006 International Conference on Computer Design

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show abstract

“…The other drawback of this scheme is that to exploit MLP fully, sophisticated compaction logic is required for the IQ to use the sparse vacant entries effectively in the small queue created by the instruction transfer. This compaction logic is extremely complex [27]. Note that the enlarged IQ only requires simple compaction logic, because inefficiency in terms of the capacity is tolerated.…”

Section: Exploiting Mlpmentioning

confidence: 99%

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

Kora

Yamaguchi

Ando

2014

IEICE Trans. Inf. & Syst.

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SUMMARYSingle-thread performance has not improved much over the past few years, despite an ever increasing transistor budget. One of the reasons for this is that there is a speed gap between the processor and main memory, known as the memory wall. A promising method to overcome this memory wall is aggressive out-of-order execution by extensively enlarging the instruction window resources to exploit memory-level parallelism (MLP). However, simply enlarging the window resources lengthens the clock cycle time. Although pipelining the resources solves this problem, it in turn prevents instruction-level parallelism (ILP) from being exploited because issuing instructions requires multiple clock cycles. This paper proposed a dynamic scheme that adaptively resizes the instruction window based on the predicted available parallelism, either ILP or MLP. Specifically, if the scheme predicts that MLP is available during execution, the instruction window is enlarged and the window resources are pipelined, thereby exploiting MLP. Conversely, if the scheme predicts that less MLP is available, that is, ILP is exploitable for improved performance, the instruction window is shrunk and the window resources are de-pipelined, thereby exploiting ILP. Our evaluation results using the SPEC2006 benchmark programs show that the proposed scheme achieves nearly the best performance possible with fixed-size resources. On average, our scheme realizes a performance improvement of 21% over that of a conventional processor, with additional cost of only 6% of the area of the conventional processor core or 3% of that of the entire processor chip. The evaluation results also show 8% better energy efficiency in terms of 1/EDP (energy-delay product).

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“…As comparison, the issue logic of the Compaq Alpha 21264 processor, a 4-way superscalar RISC processor, contains about 141000 transistors [15], making the complexity of our modifications negligible.…”

Section: Complexity and Delay Of Control Path Modificationsmentioning

confidence: 99%

Validating Word-Oriented Processors for Bit and Multi-word Operations

Lee

Yang

Shi

2004

Advances in Computer Systems Architecture

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Abstract. We examine secure computing paradigms to identify any new architectural challenges for future general-purpose processors. Some essential security functions can be provided by different classes of cryptography algorithms. We identify two categories of operations in these algorithms that are not common in previous general-purpose workloads: bit operations within a word and multi-word operations. Both challenge the basic word orientation of processors. We show how very complex bit-level operations, namely arbitrary bit permutations within a word, can be achieved in O(1) cycles, rather than O(n) cycles as in existing RISC processors. We describe two solutions: one using only microarchitecture changes, and another with Instruction Set Architecture (ISA) support. We generalize our solutions to define datarich execution with MOMR (Multi-word Operands Multi-word Result) functional units. This can address both challenges, leveraging available resources in typical processors with minimal additional cost. Thus we validate the basic word-orientation of processor architectures, since they can also provide superior performance for both bit and multi-word operations needed by cryptographic processing.

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Issue logic for a 600-MHz out-of-order execution microprocessor

Cited by 69 publications

References 2 publications

An Enhancement for a Scheduling Logic Pipelined over two Cycles

An Enhancement for a Scheduling Logic Pipelined over two Cycles

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

Validating Word-Oriented Processors for Bit and Multi-word Operations

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