An Enhancement for a Scheduling Logic Pipelined over two Cycles

Abstract

-Out of order processors use the dynamic scheduling logic both to expose and to exploit parallelism. Pipelining this logic may sacrifice the ability to execute dependent instructions in consecutive cycles. Several previous studies have shown that pipelining the scheduling logic over two cycles degrades performance; our evaluations, in a 4-way machine, on SPEC-2000 integer benchmarks show a performance degradation about 11% compared to an unpipelined scheduling logic.In this work, we present two non-speculative enhancements for a scheduling logic pipelined over two cycles. The idea is computing in advance which instructions will be woken-up by all instructions that are currently competing for selection. Once all of them have been selected, the pre-computed group of instructions can compete for selection in next cycle. The enhancement goal is to tolerate the scheduling-loop latency when not enough ILP is available through the scheduling of dependent instructions in consecutive cycles.Our results in a 4-way machine show that our two proposed enhancements perform, on average, slightly better than two previously proposed speculative schedulers. The performance of our proposals is within a 2.6% and 2% of an unpipelined ideal scheduler.Index Terms -Back-to-back execution, dynamic scheduler, pipelined scheduling logic.

On reducing misspeculations in a pipelined scheduler

“…There exists an opportunity to execute back-to-back dependent instructions when all instructions of the parent group of onecycle instructions have been selected. While [31] is speculative, [11] is not. Moreover, both proposals use two Wakeup Logics which duplicate the cost of the wakeup phase.…”

“…An additional Wakeup Logic driven by parent instructions confirms if each selected instruction has their source operands available. R. Gran et al [11] add a Wakeup Logic to a base two-cycle scheduling logic in order to detect opportunities to execute dependent instructions back-to-back. This added Wakeup Logic keeps instructions dependent on one-cycle instructions; they are woken up when the parent group of one-cycle instructions starts competing for selection.…”

“…While some of these proposals allow the consumer-level to compete for selection speculatively [31] or to issue speculatively [4], other proposal does not rely on speculation [11]. Also, while proposals [11] and [31] require two logical Wakeup Matrices to wakeup dependent instructions, proposal [4] requires only one Wakeup Matrix.…”

“…As DLS mechanism is not speculative, both false selections [31] and pileup victims [4] are avoided. Moreover, DLS mechanism, as SelectFree, requires one Wakeup Matrix, in contrast with [11] and [31] which require two logical Wakeup Matrices. As we describe in the evaluation section, we consider load-latency prediction and memory dependence prediction in contrast to [4] [11] and [31].…”

“…Moreover, DLS mechanism, as SelectFree, requires one Wakeup Matrix, in contrast with [11] and [31] which require two logical Wakeup Matrices. As we describe in the evaluation section, we consider load-latency prediction and memory dependence prediction in contrast to [4] [11] and [31]. We compare DLS mechanism with Select-Free mechanism, which hardware costs are similar, and we show that DLS mechanism is outperformed by Select-Free, on average, by 0.3%.…”