Is high level synthesis ready for business? A computational finance case study

Inggs, Gordon; Fleming, Shane T.; Thomas, David B.; Luk, Wayne

doi:10.1109/fpt.2014.7082747

Cited by 20 publications

(10 citation statements)

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“…In the last few years, High-Level Synthesis (HLS) tools have demonstrated considerable progress in generating FPGA-based hardware designs from a high level of abstraction [39]. Existing tools such as Xilinx's Vivado HLS, Intel FPGA OpenCL SDK, Maxeler's MaxCompiler and LegUp [8] employ commonly used programming languages such as C, C++, OpenCL and Java in order to facilitate the development of functionally correct hardware designs.…”

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confidence: 99%

Toolflows for Mapping Convolutional Neural Networks on FPGAs

2018

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In the past decade, Convolutional Neural Networks (CNNs) have demonstrated state-of-the-art performance in various Artificial Intelligence tasks. To accelerate the experimentation and development of CNNs, several software frameworks have been released, primarily targeting power-hungry CPUs and GPUs. In this context, reconfigurable hardware in the form of FPGAs constitutes a potential alternative platform that can be integrated in the existing deep learning ecosystem to provide a tunable balance between performance, power consumption and programmability. In this paper, a survey of the existing CNN-to-FPGA toolflows is presented, comprising a comparative study of their key characteristics which include the supported applications, architectural choices, design space exploration methods and achieved performance. Moreover, major challenges and objectives introduced by the latest trends in CNN algorithmic research are identified and presented. Finally, a uniform evaluation methodology is proposed, aiming at the comprehensive, complete and in-depth evaluation of CNN-to-FPGA toolflows. ACM Reference format: Stylianos I. Venieris, Alexandros Kouris and Christos-Savvas Bouganis. 2018. Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions. ACM Comput. Surv. 0, 0, Article 0 (March 2018), 36 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn INTRODUCTIONConvolutional Neural Networks (CNNs) [47] have demonstrated remarkable performance in Artificial Intelligence (AI) tasks. Being able to achieve high accuracy and frequently outperform traditional AI approaches, CNNs have been employed in a vast range of applications over the last decade, from object detection [72][53] and classification [78][82] to drone navigation [20] and autonomous driving [11] [7]. While becoming the state-of-the-art algorithm in AI fields such as machine vision, CNNs are challenged to deal with tasks of continuously increasing complexity. This leads to the design of deeper, more expressive networks at the expense of an increase in computational and memory requirements.

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confidence: 99%

Toolflows for Mapping Convolutional Neural Networks on FPGAs

2018

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“…The difference, however, was in the logic utilization and performance. Similarly, the authors in [121], compare the same aforementioned list of compilers quantitatively and qualitatively using several financial engineering problems (e.g., Monte Carlo-based Option Pricing) and compare the performance of several FPGA boards. Their results show that both Intel FPGA SDK for OpenCL and MaxCompiler performed better than Vivado HLS due to their ability to extract parallelism more effectively.…”

Section: A High Level Synthesis (Hls)mentioning

confidence: 99%

Software-defined Radios: Architecture, state-of-the-art, and challenges

Akeela

Dezfouli

2018

Computer Communications

111

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Software-defined Radio (SDR) is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware. Progress in the SDR field has led to the escalation of protocol development and a wide spectrum of applications, with more emphasis on programmability, flexibility, portability, and energy efficiency, in cellular, WiFi, and M2M communication. Consequently, SDR has earned a lot of attention and is of great significance to both academia and industry. SDR designers intend to simplify the realization of communication protocols while enabling researchers to experiment with prototypes on deployed networks. This paper is a survey of the state-of-theart SDR platforms in the context of wireless communication protocols. We offer an overview of SDR architecture and its basic components, then discuss the significant design trends and development tools. In addition, we highlight key contrasts between SDR architectures with regards to energy, computing power, and area, based on a set of metrics. We also review existing SDR platforms and present an analytical comparison as a guide to developers. Finally, we recognize a few of the related research topics and summarize potential solutions.

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“…Modern FPGAs are being used as hardware accelerators because they contain millions of uncommitted logic elements, hardened PCIe interfaces, and can achieve peak performance over several GFLOPs thanks to dedicated floating point resources [5]. This high throughput results in hard requirements on the memory bandwidth and the corresponding interfaces.…”

Section: Related Workmentioning

confidence: 99%