Is Formal Verification Bound to Remain a Junior Partner of Simulation?

Abstract

Abstract. After decades of research the late eighties and the nineties have produced a number of "checkers" verifying complex aspects of industrial designs and thus raising the attention of early adopters. These achievements, however, have not led to wide adoption. The generally accepted explanation of this resistance is the required methodology change and the lacking ease of use. We see a more fundamental reason in the difficulty to set up a compelling value proposition based on isolated proven theorems.With the advent of assertion-based verification the first two of the above obstacles are being successfully tackled. In this framework formal verification is piggybacking on advanced and established simulation platforms.We foresee as a next step in the evolution of formal verification fully formal solutions for important functional verification tasks. Similar to formal equivalence checking these solutions will excel by extreme quality and improved productivity. This claim is exemplified by reporting about the formal verification of an industrial embedded processor within a large national initiative involving industry and academia.

A generic implementation model for the formal verification of networks-on-chips

“…This approach has been very successful. Simple industrial designs can be fully verified, and the verification effort is largely automatic [2]. Today, systems-on-chips are multi-processors and their functional correctness largely depends on the correctness of the communication architecture [4].…”

Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter

“…A component abstraction is built from these properties and environment assumptions. Büttner [8] adopts a similar method with CTL properties in the context of synchronized module composition. Its abstract model of module is well suited to provide a cycle accurate abstraction to be used in microarchitecture verification.…”