A generic implementation model for the formal verification of networks-on-chips

Abstract

Formal verification often means the proof of a formal relation between abstract specification models and concrete implementation models. For microprocessor designs, commutative diagrams derived from these models and relations have been very successful. In the context of communication modules, no such diagram exists. The generic networkon-chip model (GeNoC) has been recently proposed as a generic specification model to validate high-level descriptions of networks-on-chips. We report on work in progress towards the definition of a generic verification diagram based on GeNoC. We present a generic model for implementations. Following the GeNoC approach, our new model is generic in the sense that it characterizes a large family of designs and that the validation of a concrete implementation consists in proving it a valid instance of the generic model. In the paper, we detail the implementation of packet and circuit switching techniques. We report on other instances which support the generic character of our model.

Formal validation of deadlock prevention in networks-on-chips

“…In another submission [17], we developed a generic implementation modelà la GeNoC. We are currently working on the proof of a formal relation between this GeNoC implementation model and the GeNoC specification model presented in this paper.…”

Towards a formally verified network-on-chip

“…In the implementation, routing decisions are distributed over each individual node, i.e., hop-by-hop. Details of the implementation model are available [14]. The original contribution of this paper consists of the definition of the specification model and the proof that the implementation behaves according to its specification for a 2D-mesh network based on the HERMES NoC [10].…”