2009 Formal Methods in Computer-Aided Design 2009
DOI: 10.1109/fmcad.2009.5351124
|View full text |Cite
|
Sign up to set email alerts
|

Towards a formally verified network-on-chip

Abstract: Multi-Processor Systems-on-Chip (MPSoC) designs are constructed by assembling pre-designed parameterized components. Communications are crucial to their overall functionality and performance. Formal verification methods have been intensively applied to processing elements, e.g., microprocessors. Very little work has been done with respect to communication modules. We present the formal specification of a packet switched NoC and its proven refinement. At the specification level, routing decisions are computed a… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

2010
2010
2017
2017

Publication Types

Select...
2
1

Relationship

1
2

Authors

Journals

citations
Cited by 3 publications
(2 citation statements)
references
References 12 publications
(11 reference statements)
0
2
0
Order By: Relevance
“…The GeNoC model used in this paper is at the specification level. Recently, van den Broek and Schmaltz [22] defined two variations (implementation and specification) of the GeNoC model and formally proved them equivalent. We plan to integrate our deadlock and evacuation theorems to these new models and their relation contributing to a general cross-layer verification method for NoCs.…”
Section: Discussionmentioning
confidence: 99%
“…The GeNoC model used in this paper is at the specification level. Recently, van den Broek and Schmaltz [22] defined two variations (implementation and specification) of the GeNoC model and formally proved them equivalent. We plan to integrate our deadlock and evacuation theorems to these new models and their relation contributing to a general cross-layer verification method for NoCs.…”
Section: Discussionmentioning
confidence: 99%
“…A general survey of formal verification in hardware design can be seen at [6]. Some sample works in hardware verification in networking include verification of: i the lookup machine of a hardware router [222], ii the Fairisle ATM swithing element [223], iii) network-on-chip [224] [225].…”
Section: ) Declarative Network Verificationmentioning
confidence: 99%