Towards a formally verified network-on-chip

Broek, T. van den; Schmaltz, Julien

doi:10.1109/fmcad.2009.5351124

Cited by 3 publications

(2 citation statements)

References 12 publications

(11 reference statements)

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“…The GeNoC model used in this paper is at the specification level. Recently, van den Broek and Schmaltz [22] defined two variations (implementation and specification) of the GeNoC model and formally proved them equivalent. We plan to integrate our deadlock and evacuation theorems to these new models and their relation contributing to a general cross-layer verification method for NoCs.…”

Section: Discussionmentioning

confidence: 99%

Formal specification of networks-on-chips: deadlock and evacuation

Verbeek¹,

Schmaltz²

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Networks-on-chips (NoC) are emerging as a promising interconnect solution for efficient Multi-Processors Systemson-Chips. We propose a methodology that supports the specification of parametric NoCs. We provide sufficient constraints that ensure deadlock-free routing, functional correctness, and liveness of the design. To illustrate our method, we discharge these constraints for a parametric NoC inspired by the HERMES architecture.

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Section: Discussionmentioning

confidence: 99%

Formal specification of networks-on-chips: deadlock and evacuation

Verbeek¹,

Schmaltz²

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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“…A general survey of formal verification in hardware design can be seen at [6]. Some sample works in hardware verification in networking include verification of: i the lookup machine of a hardware router [222], ii the Fairisle ATM swithing element [223], iii) network-on-chip [224] [225].…”

Section: ) Declarative Network Verificationmentioning

confidence: 99%

Applying Formal Methods to Networking: Theory, Techniques, and Applications

Qadir

Hasan

2015

IEEE Commun. Surv. Tutorials

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Despite its great importance, modern network infrastructure is remarkable for the lack of rigor in its engineering. The Internet which began as a research experiment was never designed to handle the users and applications it hosts today. The lack of formalization of the Internet architecture meant limited abstractions and modularity, especially for the control and management planes, thus requiring for every new need a new protocol built from scratch. This led to an unwieldy ossified Internet architecture resistant to any attempts at formal verification, and an Internet culture where expediency and pragmatism are favored over formal correctness. Fortunately, recent work in the space of clean slate Internet designespecially, the software defined networking (SDN) paradigmoffers the Internet community another chance to develop the right kind of architecture and abstractions. This has also led to a great resurgence in interest of applying formal methods to specification, verification, and synthesis of networking protocols and applications. In this paper, we present a self-contained tutorial of the formidable amount of work that has been done in formal methods, and present a survey of its applications to networking.

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Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture

Daoud

Tanougast

Belarbi

et al. 2017

Systems

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Abstract:Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC) design. To achieve this, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in the validation process. The Event-B method is a promising formal approach that can be used to develop, model and prove accurately SoC and MPSoC architectures. This paper proposes a formal verification approach for NoC architecture including the dependability constraints relating to the choice of the path routing of data packets and the strategy imposed for diversion when faulty routers are detected. The formalization process is incremental and validated by correct-by-construction development of the NoC architecture. Using the concepts of graph colouring and B-event formalism, the results obtained have demonstrated its efficiency for determining the bugs, and a solution to ensure a fast and reliable operation of the network when compared to existing similar methods.

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Towards a formally verified network-on-chip

Cited by 3 publications

References 12 publications

Formal specification of networks-on-chips: deadlock and evacuation

Formal specification of networks-on-chips: deadlock and evacuation

Applying Formal Methods to Networking: Theory, Techniques, and Applications

Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture

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