Abstract:In this paper, we present a new approach for estimating the one-diode model parameters of a photovoltaic solar panel according to the irradiance and temperature. These parameters are given, at a known irradiance and temperature, from the knowledge of three operating points: short circuit, open circuit, and maximum power. In the first step, the adopted approach concerns the resolution of the system of equations constituting the three operating points to write all the model parameters according to series resistance. Secondly, we make an iterative resolution at the optimal operating point by using the Newton-Raphson method to calculate the series resistance value as well as the model parameters.Once the last ones are identified, we consider other equations for taking into account the irradiance and temperature effect. The simulation results show the convergence speed of the model parameters and the possibility of visualizing the electrical behavior of the panel according to the irradiance and temperature. With the identified model, we can develop algorithms of maximum power point tracking and make simulations of PV systems.
Event-B is the promising approach applied on several domains, it can be used to specify, prove and develop SoCs and MPSoCs models incrementally using the refinement . The suggested new refinement approach consists of suggesting new concepts and constraints related to the reliabilit y of QNoCs and the over-cost related to the solutions of FPGA-Based technology fault-tolerance in the reason of practically managing the comple xit y caused by the extremely large number of variables used in the VHDL code (last step of the refinement) which are describing the state of QNoC systems. To remediate to this problem, we introduce concepts of decomposition and Re-composition that use three new operat ors (Rename, Enrich, Ensure) that they are linking together and used to enhance the Event-B refinement to finally make it more and more structural.
Abstract:Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC) design. To achieve this, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in the validation process. The Event-B method is a promising formal approach that can be used to develop, model and prove accurately SoC and MPSoC architectures. This paper proposes a formal verification approach for NoC architecture including the dependability constraints relating to the choice of the path routing of data packets and the strategy imposed for diversion when faulty routers are detected. The formalization process is incremental and validated by correct-by-construction development of the NoC architecture. Using the concepts of graph colouring and B-event formalism, the results obtained have demonstrated its efficiency for determining the bugs, and a solution to ensure a fast and reliable operation of the network when compared to existing similar methods.
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