A new operators-based approach for the Event-B refinement: QNoC case study

Abstract

Event-B is the promising approach applied on several domains, it can be used to specify, prove and develop SoCs and MPSoCs models incrementally using the refinement . The suggested new refinement approach consists of suggesting new concepts and constraints related to the reliabilit y of QNoCs and the over-cost related to the solutions of FPGA-Based technology fault-tolerance in the reason of practically managing the comple xit y caused by the extremely large number of variables used in the VHDL code (last step of the refinement) which are describing the state of QNoC systems. To remediate to this problem, we introduce concepts of decomposition and Re-composition that use three new operat ors (Rename, Enrich, Ensure) that they are linking together and used to enhance the Event-B refinement to finally make it more and more structural.

The Event-B Modelling with Operators-based Refinement of NoC-based Wireless Sensors Networks

“…All these previous works miss the details during the coverage of embedded systems properties and constraints. Therefore it must mentioned that some current works used RODIN tool-set to formalize the different actions inside this self-recovering network [38] when others try to use Event-B models to validate the distributed systems [10,19,39]. In this context, Various studies have focused on the high-level architecture descriptions ( [40][41][42][43][44][45][46][47][48][49][50][51]).…”

“…Event-B is a formal method based on the B method [8] provides the toolset RODIN [9,10] to carry out of specifications, refinements and proofs ( [11,12]) in Event-B. However, one of the goals of this paper is to make the Event-B may allow executable code generation, where the specifications have implementation details based on the notion of theory (theory Plug-in) to express NoC desired properties of the XY routing algorithm presented by the VHDL code behaviour.…”

Formal and Informal Modeling of Fault Tolerant Noc Architectures

“…During design process we have to add new elements (functions) to an existing system: incrementality notion [7]. Research works which deal the complexity process of incrementality versus refinement by introducing the notion of pre-validated types like graph theory are for example [6,8,9,10], that try to decrease specification complexity. In the case of this paper, there are several phases of implementation which we exploit to improve the system by optimizing our architecture.…”