Formal verification of circuit-switched Network on chip (NoC) architectures using SPIN

Zaman, Anam; Hasan, Osman

doi:10.1109/issoc.2014.6972449

Cited by 7 publications

(4 citation statements)

References 24 publications

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“…Using formal methods, [Zaman 2015] proposes a functional and performance analysis of two types of NoC: circuit switched NoC and packet switched NoC. HERMES is the chosen packet-switched NoC, while, the Programmable NoC (PNoC) [Zaman 2015] was chosen as a circuit switched NoC. Properties such as mutual exclusion, starvation freedom, deadlock and livelock have been verified using the SPIN model checker.…”

Section: Formal Verificationmentioning

confidence: 99%

Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems

Dridi

Rubini

Lallali

et al. 2019

J. Emerg. Technol. Comput. Syst.

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A Mixed Criticality System (MCS) combines real-time software tasks with different criticality levels. In a MCS, the criticality level specifies the level of assurance against system failure. For high-critical flows of messages, it is imperative to meet deadlines; otherwise, the whole system might fail, leading to catastrophic results, like loss of life or serious damage to the environment. In contrast, low-critical flows may tolerate some delays. Furthermore, in MCS, flow performances such as the Worst Case Communication Time (WCCT) may vary depending on the criticality level of the applications. Then execution platforms must provide different operating modes for applications with different levels of criticality. To conclude, in Network-On-Chip (NoC), sharing resources between communication flows can lead to unpredictable latencies and subsequently turns the implementation of MCS in many-core architectures challenging. In this article, we propose and evaluate a new NoC router to support MCS based on an accurate WCCT analysis for high-critical flows. The proposed router, called Double Arbiter and Switching router (DAS), jointly uses Wormhole and Store And Forward communication techniques for low- and high-critical flows, respectively. It ensures that high-critical flows meet their deadlines while maximizing the bandwidth remaining for the low-critical flows. We also propose a new method for high-critical communication time analysis, applied to Store And Forward switching mode with virtual channels. For low-critical flows communication time analysis, we adapt an existing wormhole communication time analysis with share policy to our context. The second contribution of this article is a multi-abstraction-level evaluation of DAS. We evaluate the communication time of flows, the system mode change, the cost, and four properties of DAS. Simulations with a cycle-accurate SystemC NoC simulator show that, with a 15% network use rate, the communication delay of high-critical flows is reduced by 80% while communication delay of low-critical flow is increased by 18% compared to solutions based on routers with multiple virtual channels. For 10% of network interferences, using system mode change, DAS reduces the high-critical communication delays about 66%. We synthesize our router with a 28nm SOI technology and show that the size overhead is limited of 2.5% compared to the solution based on virtual channel router. Finally, we applied model checking verification techniques to automatically prove several DAS properties required by critical systems designers.

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Section: Formal Verificationmentioning

confidence: 99%

Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems

Dridi

Rubini

Lallali

et al. 2019

J. Emerg. Technol. Comput. Syst.

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“…A valid path implies that packets are routed only through the routers that are part of the mesh network. In another work [9], authors used PROMELA to specify Programmable Network-On-Chip (PNOC), which is a circuit, switched NOC architecture. The topology contains series of subnets where multiple nodes are connected to a single router through the router port interfaces.…”

Section: Promelamentioning

confidence: 99%

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Boutekkouk

2018

Int. J. Recent Contrib. Eng. Sci. IT

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Network-On-Chip (NOC) is an emerging paradigm to surmount traditional bus based Systems-On-Chip (SOC) limits especially scalability and communication performances. A NOC includes many applications that can execute concurrently. This situation may show some undesirable behaviors such as deadlock, livelock, starvation, etc. On the other hand, the application of formal methods to on-chip communication infrastructures has recieved more attention. Formal analysis of NOC communication will be very advantageous since it allows proving some theorems or interesting qualitative/quantitative properties on the communication behavior where simulation/emulation techniques can fail easily. In this paper we try to giva an overview of the most famous formal methods applied to the verification of communication inside NOCs.

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“…Existing literature lacks probabilistic verification of the NoC. NoC formal verification has focused primarily on functional correctness [1][2][3][4], checking performance [5][6][7], and security [8,9]. Advances in probabilistic verification have produced mature tools such as the Modest Toolset [10], which includes the mcsta probabilistic model checker and the modes statistical model checker [11], Storm [12], and PRISM [13].…”

Section: Introductionmentioning

confidence: 99%

Probabilistic Verification for Reliability of a Two-by-Two Network-on-Chip System

Roberts

Lewis

Hartmanns

et al. 2021

Formal Methods for Industrial Critical Systems

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Modern network-on-chip (NoC) systems face reliability issues due to process and environmental variations. The power supply noise (PSN) in the power delivery network of a NoC plays a key role in determining reliability. PSN leads to voltage droop, which can cause timing errors in the NoC. This paper makes a novel contribution towards formally analyzing PSN in NoC systems. We present a probabilistic model checking approach to analyze key features of PSN at the behavioral level in a 2 × 2 mesh NoC with a uniform random traffic load. To tackle state explosion, we apply incremental abstraction techniques, including a novel probabilistic choice abstraction, based on observations of NoC behavior. The Modest Toolset is used for probabilistic modeling and verification. Results are obtained for several flit injection patterns to reveal their impacts on PSN. Our analysis finds an optimal flit pattern generation with zero probability of PSN events and suggests spreading flits rather than releasing them in consecutive cycles in order to minimize PSN.

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Formal verification of circuit-switched Network on chip (NoC) architectures using SPIN

Cited by 7 publications

References 24 publications

Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems

Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Probabilistic Verification for Reliability of a Two-by-Two Network-on-Chip System

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