Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)
DOI: 10.1109/rsp.2006.19
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Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter

Abstract: This work studies the relations between pipeline architectures and their specification expressed in CTL. We propose a method to build pipeline structures incrementally from a simple one (already verified) to a more complex one. Moreover, we show how each increment can be integrated in a CTL specification. We define increments to model treatment delay and treatment abortion of a pipeline flow, and we formalize the composition of the different increments. In order to represent the increments added to an architec… Show more

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