Is a New Paradigm for Nanoscale Analog CMOS Design Needed?

Lewyn, L.L.; Williams, Nicolas

doi:10.1109/jproc.2010.2083810

Cited by 9 publications

(6 citation statements)

References 1 publication

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“…Designing neural amplifiers, or any analog integrated circuit, in such fine-line, CMOS processes hold numerous challenges, including increased gate and channel leakage [111], increased flicker noise [21, 140] and increased intradie variability [13, 50]. There are more process-related design constraints that must be considered compared to the other mature industrial process technologies [69, 70, 147, 148]. Hence, it may seem that neural amplifiers would not benefit from this continuous CMOS process scaling.…”

Section: Applications Of Neural Amplifiersmentioning

confidence: 99%

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Greenwald

et al. 2016

Med Biol Eng Comput

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Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

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Section: Applications Of Neural Amplifiersmentioning

confidence: 99%

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Greenwald

et al. 2016

Med Biol Eng Comput

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“…Additionally, the AMG creates symmetric device structures, like commoncentroid and interdigitated layout styles, which are particularly helpful in reducing mismatch errors and the effects of thermal gradients on-die reducing the gap between pre-and post-layout simulation [12]. Other device structures, like the technique proposed in [12] to reduce the pre-to post-layout STI stress effect related mismatch could be included in the AMG to further increase the robustness of the solution. The idea behind this technique is to limit the number of fingers to 2 for each stack, hence fixing the values for the SA, SB and SD transistor model parameters defined in BSIM4 [30], shown in Fig.…”

Section: Analog Module Generatormentioning

confidence: 99%

“…In our approach, instead of the time-consuming complete layout generation and extraction to control the parasitic effects, the undesirable layout induced effects are alleviated by using the designer experience to define using simple constructs where and how to lay out the devices. By enforcing matching, symmetry and proximity constraints on the individual devices, and by further increasing matching using complex layout structures like common-centroid or interdigitated [10], the deviations due the fabrications process, as observed in [11], are reduced thus shortening the gap between pre-and post-layout circuit simulation [12]. The new circuit optimizer, AIDA-C, which evolved from GENOM-POF [13] in the AIDA framework [14], implements the proposed floorplan-aware automatic synthesis flow and is used to demonstrate its effectiveness.…”

Section: Introductionmentioning

confidence: 99%

Floorplan-aware analog IC sizing and optimization based on topological constraints

et al. 2015

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“…Several works, such as [8], [9], [10] and [11], target the automation of the layout generation of analog circuits.…”

Section: ) the Shallow Trench Isolation (Sti)mentioning

confidence: 99%

A Python-based layout-aware analog design methodology for nanometric technologies

Youssef

Javid

Dupuis

et al. 2011

2011 IEEE 6th International Design and Test Workshop (IDT)

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Abstract-This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The procedural layout description is written using a Python API that ensures layout portability over different technologies. A main focus is on how the layout generation tool addresses both geometric and parasiticaware electrical synthesis. This is made possible through an internal loop that links circularly both the sizing phase and the layout generation phase. The proposed design methodology assists the analog designer in exploring electrical and physical trade-offs. At the end, we present synthesis and characterization results that prove the effectiveness and speed of the proposed methodology.

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Is a New Paradigm for Nanoscale Analog CMOS Design Needed?

Cited by 9 publications

References 1 publication

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Floorplan-aware analog IC sizing and optimization based on topological constraints

A Python-based layout-aware analog design methodology for nanometric technologies

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