IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

Zergainoh, Nacer-Eddine; Popovici, Katalin; Jerraya, A.A.; Urard, Pascal

doi:10.1109/aspdac.2005.1466236

Cited by 5 publications

(3 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We applied the ADCM and associated IP-based design flow to synthetic example (previously presented) and three high-throughput dedicated DSP systems: digital modulation chain circuit extracted from a real design of TV digital transmission satellite application [5], turbo decoder based on the soft output viterbi algorithm (SOVA), MP3 (MPEG-1 Audio Layer-3) audio compression standard. Functional and RTL models of these three applications were built by assembling the various predesigned and prevalidated IPs.…”

Section: Resultsmentioning

confidence: 99%

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

Zergainoh

Tambour²,

Jerraya³

2006

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

The Intellectual Property (IP)-based design for highthroughput dedicated digital signal processing (DSP) systems is obviously an important issue for improving not only design productivity, but also design from the high level of abstraction. However, in some cases, synthesizable register transfer level (RTL) model obtained by an automatic assembly of RTL IPs can be wrong due to delays induced by implementation constraints. In this paper, we present the formalization of the problem and propose an approach called automatic delay correction method (ADCM) to solve the problem without inserting an extra interface circuitry. The approach automatically inserts control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IPs. The delays may be managed by registers or by counters included in the control structure. A formal theory of ADCM is developed to guide the implementation and guarantee optimal solutions in latency and area. Through experiments with synthetic example and three real world high-throughput DSP circuits, we also show the effectiveness of our approach.Index Terms-Delay correction method, digital signal processing (DSP) VLSI systems, finite state machine (FSM) modification and register insertion, generic functional and register transfer level (RTL) IPs, hardware synthesis, Intellectual Property (IP)-based design.

show abstract

Section: Resultsmentioning

confidence: 99%

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

Zergainoh

Tambour²,

Jerraya³

2006

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…The IP-based design methodology is based on designer's practice [28,29]. The methodology, described in Figure 1, generates register-transfer-level (RTL) architecture starting from a functional model, given in Matlab.…”

Section: Overview Of Design Methodologymentioning

confidence: 99%

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

Zergainoh

Tambour

Urard

et al. 2006

EURASIP J. Adv. Signal Process.

View full text Add to dashboard Cite

We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

show abstract

“…IP reuse is one type of design reuse and it helps to address the gap between the capacity for design complex system and productivity [Gajski 1999]. IP modules are used for improving productivity in [Zergainoh et al 2005]. In [Hekmatpour et al 2005], a methodology is described for IP design and integration.…”

Section: Introductionmentioning

confidence: 99%

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Mao

Chen

Zhang

et al. 2016

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

While traditional Field-Programmable Gate Array design flow usually employs fine-grained tile-based placement, modular placement is increasingly required to speed up the large-scale placement and save the synthesis time. Moreover, the commonly used modules can be pre-synthesized and stored in the library for design reuse to significantly save the design, verification time, and development cost. Previous work mainly focuses on modular floorplanning without module placement information. In this article, we propose a library-based placement and routing flow that best utilizes the pre-placed and routed modules from the library to significantly save the execution time while achieving the minimal area-delay product. The flow supports the static and reconfigurable modules at the same time. The modular information is represented in the B*-Tree structure, and the B*-Tree operations are amended together with Simulated Annealing to enable a fast search of the placement space. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Partial reconfiguration-aware routing using pin-to-wire abutment is proposed to connect the modules after placement. Our placer can reduce the compilation time by 65% on average with 17% area and 8.2% delay overhead compared with the fine-grained results of Versatile Place and Route through the reuse of module information in the library for the base architecture. For other architectures, the area increase ranges from 8.32% to 25.79%, the delay varies from − 13.66% to 19.79%, and the runtime improves by 43.31% to 77.2%.

show abstract

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

Cited by 5 publications

References 14 publications

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Contact Info

Product

Resources

About